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Bibliographic Details
Main Authors: Babaee, Ramin, Gharan, Shahab Oveis, Bouchard, Martin
Format: Preprint
Published: 2025
Subjects:
Online Access:https://arxiv.org/abs/2505.18353
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Table of Contents:
  • We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random current mismatches. Unlike binary, thermometer-coded, and segmented DACs, the current weights of the proposed architecture are not an integer power of 2 or any other integer number. We present a heuristic algorithm for a static mapping of DAC input codewords into corresponding DAC switches. High-level Matlab simulations are performed to illustrate the static performance improvement over the segmented structure.