CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
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arXiv
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| Autores principales: | , , , , , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2025
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| _version_ | 1866915303288471552 |
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| author | Oh, Dongsuk Kwon, Miryeong Kim, Jiseon Na, Eunjee Moon, Junseok Choi, Hyunkyu Jang, Seonghyeon Choi, Hanjin Jung, Hongjoo Lee, Sangwon Jung, Myoungsoo |
| author_facet | Oh, Dongsuk Kwon, Miryeong Kim, Jiseon Na, Eunjee Moon, Junseok Choi, Hyunkyu Jang, Seonghyeon Choi, Hanjin Jung, Hongjoo Lee, Sangwon Jung, Myoungsoo |
| contents | Integrating compute express link (CXL) with SSDs allows scalable access to large memory but has slower speeds than DRAMs. We present ExPAND, an expander-driven CXL prefetcher that offloads last-level cache (LLC) prefetching from host CPU to CXL-SSDs. ExPAND uses a heterogeneous prediction algorithm for prefetching and ensures data consistency with CXL.mem's back-invalidation. We examine prefetch timeliness for accurate latency estimation. ExPAND, being aware of CXL multi-tiered switching, provides end-to-end latency for each CXL-SSD and precise prefetch timeliness estimations. Our method reduces CXL-SSD reliance and enables direct host cache access for most data. ExPAND enhances graph application performance and SPEC CPU's performance by 9.0$\times$ and 14.7$\times$, respectively, surpassing CXL-SSD pools with diverse prefetching strategies. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_18577 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance Oh, Dongsuk Kwon, Miryeong Kim, Jiseon Na, Eunjee Moon, Junseok Choi, Hyunkyu Jang, Seonghyeon Choi, Hanjin Jung, Hongjoo Lee, Sangwon Jung, Myoungsoo Hardware Architecture Integrating compute express link (CXL) with SSDs allows scalable access to large memory but has slower speeds than DRAMs. We present ExPAND, an expander-driven CXL prefetcher that offloads last-level cache (LLC) prefetching from host CPU to CXL-SSDs. ExPAND uses a heterogeneous prediction algorithm for prefetching and ensures data consistency with CXL.mem's back-invalidation. We examine prefetch timeliness for accurate latency estimation. ExPAND, being aware of CXL multi-tiered switching, provides end-to-end latency for each CXL-SSD and precise prefetch timeliness estimations. Our method reduces CXL-SSD reliance and enables direct host cache access for most data. ExPAND enhances graph application performance and SPEC CPU's performance by 9.0$\times$ and 14.7$\times$, respectively, surpassing CXL-SSD pools with diverse prefetching strategies. |
| title | CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2505.18577 |