Automatic Verification of Floating-Point Accumulation Networks
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arXiv
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866910967162470400 |
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| author | Zhang, David K. Aiken, Alex |
| author_facet | Zhang, David K. Aiken, Alex |
| contents | Floating-point accumulation networks (FPANs) are key building blocks used in many floating-point algorithms, including compensated summation and double-double arithmetic. FPANs are notoriously difficult to analyze, and algorithms using FPANs are often published without rigorous correctness proofs. In fact, on at least one occasion, a published error bound for a widely used FPAN was later found to be incorrect. In this paper, we present an automatic procedure that produces computer-verified proofs of several FPAN correctness properties, including error bounds that are tight to the nearest bit. Our approach is underpinned by a novel floating-point abstraction that models the sign, exponent, and number of leading and trailing zeros and ones in the mantissa of each number flowing through an FPAN. We also present a new FPAN for double-double addition that is faster and more accurate than the previous best known algorithm. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_18791 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Automatic Verification of Floating-Point Accumulation Networks Zhang, David K. Aiken, Alex Numerical Analysis Logic in Computer Science Floating-point accumulation networks (FPANs) are key building blocks used in many floating-point algorithms, including compensated summation and double-double arithmetic. FPANs are notoriously difficult to analyze, and algorithms using FPANs are often published without rigorous correctness proofs. In fact, on at least one occasion, a published error bound for a widely used FPAN was later found to be incorrect. In this paper, we present an automatic procedure that produces computer-verified proofs of several FPAN correctness properties, including error bounds that are tight to the nearest bit. Our approach is underpinned by a novel floating-point abstraction that models the sign, exponent, and number of leading and trailing zeros and ones in the mantissa of each number flowing through an FPAN. We also present a new FPAN for double-double addition that is faster and more accurate than the previous best known algorithm. |
| title | Automatic Verification of Floating-Point Accumulation Networks |
| topic | Numerical Analysis Logic in Computer Science |
| url | https://arxiv.org/abs/2505.18791 |