Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation
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arXiv
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| Format: | Preprint |
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2025
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| author | Paria, Sudipta Ferdous, Md Rezoan Dasgupta, Aritra Chatterjee, Atri Bhunia, Swarup |
| author_facet | Paria, Sudipta Ferdous, Md Rezoan Dasgupta, Aritra Chatterjee, Atri Bhunia, Swarup |
| contents | Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-based systems, the role of scan is becoming ever more important due to its ability to make internal design nodes controllable and observable in a systematic and scalable manner. However, the effectiveness of scan-based DFT suffers from poor testability of internal nodes for complex circuits at deep logic levels. Existing solutions to address this problem primarily rely on Test Point Insertion (TPI) in the nodes with poor controllability or observability. However, TPI-based solutions, while an integral part of commercial practice, come at a high design and hardware cost. To address this issue, in this paper, we present LITE, a novel ATPG-aware lightweight scan instrumentation approach that utilizes the functional flip-flops in a scan chain to make multiple internal nodes observable and controllable in a low-cost, scalable manner. We provide both circuit-level design as well as an algorithmic approach for automating the insertion of LITE for design modifications. We show that LITE significantly improves the testability in terms of the number of patterns and test coverage for ATPG and random pattern testability, respectively, while incurring considerably lower overhead than TPI-based solutions. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_19418 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation Paria, Sudipta Ferdous, Md Rezoan Dasgupta, Aritra Chatterjee, Atri Bhunia, Swarup Hardware Architecture Emerging Technologies Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-based systems, the role of scan is becoming ever more important due to its ability to make internal design nodes controllable and observable in a systematic and scalable manner. However, the effectiveness of scan-based DFT suffers from poor testability of internal nodes for complex circuits at deep logic levels. Existing solutions to address this problem primarily rely on Test Point Insertion (TPI) in the nodes with poor controllability or observability. However, TPI-based solutions, while an integral part of commercial practice, come at a high design and hardware cost. To address this issue, in this paper, we present LITE, a novel ATPG-aware lightweight scan instrumentation approach that utilizes the functional flip-flops in a scan chain to make multiple internal nodes observable and controllable in a low-cost, scalable manner. We provide both circuit-level design as well as an algorithmic approach for automating the insertion of LITE for design modifications. We show that LITE significantly improves the testability in terms of the number of patterns and test coverage for ATPG and random pattern testability, respectively, while incurring considerably lower overhead than TPI-based solutions. |
| title | Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation |
| topic | Hardware Architecture Emerging Technologies |
| url | https://arxiv.org/abs/2505.19418 |