VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification

Fuente: arXiv

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Bibliographic Details
Main Authors:	Yubeaton, Patrick, Nakkab, Andre, Xiao, Weihua, Collini, Luca, Karri, Ramesh, Hegde, Chinmay, Garg, Siddharth
Format:	Preprint
Published:	2025
Subjects:	Programming Languages Artificial Intelligence Logic in Computer Science
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2505.20302