VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification
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arXiv
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| Main Authors: | , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866908662981722112 |
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| author | Yubeaton, Patrick Nakkab, Andre Xiao, Weihua Collini, Luca Karri, Ramesh Hegde, Chinmay Garg, Siddharth |
| author_facet | Yubeaton, Patrick Nakkab, Andre Xiao, Weihua Collini, Luca Karri, Ramesh Hegde, Chinmay Garg, Siddharth |
| contents | This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification methods to evaluate the quality and correctness of generated hardware descriptions. Additionally, we present a suite of specialized small-scale models optimized specifically for Verilog generation. Our work addresses the growing need for automated hardware design tools that can produce verifiably correct implementations from high-level specifications, potentially accelerating the hardware development process while maintaining rigorous correctness guarantees. Our code and data are available at \href{https://github.com/wilyub/VeriThoughts}{this URL}. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_20302 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification Yubeaton, Patrick Nakkab, Andre Xiao, Weihua Collini, Luca Karri, Ramesh Hegde, Chinmay Garg, Siddharth Programming Languages Artificial Intelligence Logic in Computer Science This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification methods to evaluate the quality and correctness of generated hardware descriptions. Additionally, we present a suite of specialized small-scale models optimized specifically for Verilog generation. Our work addresses the growing need for automated hardware design tools that can produce verifiably correct implementations from high-level specifications, potentially accelerating the hardware development process while maintaining rigorous correctness guarantees. Our code and data are available at \href{https://github.com/wilyub/VeriThoughts}{this URL}. |
| title | VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification |
| topic | Programming Languages Artificial Intelligence Logic in Computer Science |
| url | https://arxiv.org/abs/2505.20302 |