Cover Image

Improved Prefetching Techniques for Linked Data Structures

Fuente: arXiv

Saved in:

Bibliographic Details
Main Author:	Maruszewski, Nikola Vuk
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture C.5.3; E.1
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Sequence-Based Incremental Concolic Testing of RTL Models
by: Witharana, Hasini, et al.
Published: (2023)

A Scalable Architecture for Efficient Multi-bit Fully Homomorphic Encryption
by: Ma, Jiaao, et al.
Published: (2025)

AMC: Access to Miss Correlation Prefetcher for Evolving Graph Analytics
by: Singh, Abhishek, et al.
Published: (2024)

Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories
by: Lee, Ming-Yen, et al.
Published: (2025)

R3A: Reliable RTL Repair Framework with Multi-Agent Fault Localization and Stochastic Tree-of-Thoughts Patch Generation
by: Luo, Zizhang, et al.
Published: (2025)

A WASM-Subset Stack Architecture for Low-cost FPGAs using Open-Source EDA Flows
by: Chakrabarti, Aradhya
Published: (2025)

Mestra: Exploring Migration on Virtualized CGRAs
by: Kyriazis, Agamemnon, et al.
Published: (2026)

Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM
by: Liu, Lian, et al.
Published: (2025)

Fast and Practical Strassen's Matrix Multiplication using FPGAs
by: Ahmad, Afzal, et al.
Published: (2024)

A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions
by: Aspros, Maxime Henri, et al.
Published: (2025)

MEDEA: A Design-Time Multi-Objective Manager for Energy-Efficient DNN Inference on Heterogeneous Ultra-Low Power Platforms
by: Taji, Hossein, et al.
Published: (2025)

Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
by: Li, Mengming, et al.
Published: (2025)

FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices
by: Parameshwara, Arya, et al.
Published: (2025)

Exploring the Design Space for Message-Driven Systems for Dynamic Graph Processing using CCA
by: Chandio, Bibrak Qamar, et al.
Published: (2024)

A Survey on Hardware Accelerators for Large Language Models
by: Kachris, Christoforos
Published: (2024)

RayFlex: An Open-Source RTL Implementation of the Hardware Ray Tracer Datapath
by: Shen, Fangjia, et al.
Published: (2024)

AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security
by: Nguyen, Van Tinh, et al.
Published: (2025)

Pickle Prefetcher: Programmable and Scalable Last-Level Cache Prefetcher
by: Nguyen, Hoa, et al.
Published: (2025)

SynapticCore-X: A Modular Neural Processing Architecture for Low-Cost FPGA Acceleration
by: Parameshwara, Arya
Published: (2025)

Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning
by: Bera, Rahul, et al.
Published: (2026)

InterPUF: Distributed Authentication via Physically Unclonable Functions and Multi-party Computation for Reconfigurable Interposers
by: Tashdid, Ishraq, et al.
Published: (2026)

Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems
by: Palacios, Pedro, et al.
Published: (2024)

DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing
by: Zhang, Yuhan, et al.
Published: (2026)

Profile-Guided Temporal Prefetching
by: Li, Mengming, et al.
Published: (2025)

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm
by: Giorgi, Roberto
Published: (2025)

A Case for Kolmogorov-Arnold Networks in Prefetching: Towards Low-Latency, Generalizable ML-Based Prefetchers
by: Kulkarni, Dhruv, et al.
Published: (2025)

OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
by: Lebold, Denis, et al.
Published: (2026)

FlexiBit: Fully Flexible Precision Bit-parallel Accelerator Architecture for Arbitrary Mixed Precision AI
by: Tahmasebi, Faraz, et al.
Published: (2024)

Silent Data Corruption by 10x Test Escapes Threatens Reliable Computing
by: Mitra, Subhasish, et al.
Published: (2025)

SISA: A Scale-In Systolic Array for GEMM Acceleration
by: Altamura, Luigi, et al.
Published: (2026)

Benchmarking NIST-Standardised ML-KEM and ML-DSA on ARM Cortex-M0+: Performance, Memory, and Energy on the RP2040
by: Chhetri, Rojin
Published: (2026)

SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts
by: Prabhakar, Raghu, et al.
Published: (2024)

HERMES: High-Performance RISC-V Memory Hierarchy for ML Workloads
by: Suryadevara, Pranav
Published: (2025)

Exploring DRAM Cache Prefetching for Pooled Memory
by: Tirumalasetty, Chandrahas, et al.
Published: (2024)

Agile TLB Prefetching and Prediction Replacement Policy
by: Mersha, Melkamu, et al.
Published: (2024)

C for a tiny system
by: Krause, Philipp Klaus, et al.
Published: (2020)

Toward a Universal GPU Instruction Set Architecture: A Cross-Vendor Analysis of Hardware-Invariant Computational Primitives in Parallel Processors
by: Abraham, Ojima, et al.
Published: (2026)

Guess-Verify-Refine: Data-Aware Top-K for Sparse-Attention Decoding on Blackwell via Temporal Correlation
by: Cheng, Long, et al.
Published: (2026)

SPPAM: Signature Pattern Prediction and Access-Map Prefetcher
by: Merrell, Maccoy, et al.
Published: (2026)

ASTER: Attention-based Spiking Transformer Engine for Event-driven Reasoning
by: Das, Tamoghno, et al.
Published: (2025)