FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design

Fuente: arXiv
Saved in:
Bibliographic Details
Main Authors: Mehradfar, Asal, Zhao, Xuzhe, Huang, Yilun, Ceyani, Emir, Yang, Yankai, Han, Shihao, Aghasi, Hamidreza, Avestimehr, Salman
Format: Preprint
Published: 2025
Subjects:
Online Access:
Tags: Add Tag
No Tags, Be the first to tag this record!
_version_ 1866909872422912000
author Mehradfar, Asal
Zhao, Xuzhe
Huang, Yilun
Ceyani, Emir
Yang, Yankai
Han, Shihao
Aghasi, Hamidreza
Avestimehr, Salman
author_facet Mehradfar, Asal
Zhao, Xuzhe
Huang, Yilun
Ceyani, Emir
Yang, Yankai
Han, Shihao
Aghasi, Hamidreza
Avestimehr, Salman
contents Designing analog circuits from performance specifications is a complex, multi-stage process encompassing topology selection, parameter inference, and layout feasibility. We introduce FALCON, a unified machine learning framework that enables fully automated, specification-driven analog circuit synthesis through topology selection and layout-constrained optimization. Given a target performance, FALCON first selects an appropriate circuit topology using a performance-driven classifier guided by human design heuristics. Next, it employs a custom, edge-centric graph neural network trained to map circuit topology and parameters to performance, enabling gradient-based parameter inference through the learned forward model. This inference is guided by a differentiable layout cost, derived from analytical equations capturing parasitic and frequency-dependent effects, and constrained by design rules. We train and evaluate FALCON on a large-scale custom dataset of 1M analog mm-wave circuits, generated and simulated using Cadence Spectre across 20 expert-designed topologies. Through this evaluation, FALCON demonstrates >99% accuracy in topology inference, <10% relative error in performance prediction, and efficient layout-aware design that completes in under 1 second per instance. Together, these results position FALCON as a practical and extensible foundation model for end-to-end analog circuit design automation.
format Preprint
id arxiv_https___arxiv_org_abs_2505_21923
institution arXiv
publishDate 2025
record_format arxiv
spellingShingle FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design
Mehradfar, Asal
Zhao, Xuzhe
Huang, Yilun
Ceyani, Emir
Yang, Yankai
Han, Shihao
Aghasi, Hamidreza
Avestimehr, Salman
Machine Learning
Artificial Intelligence
Hardware Architecture
Computational Engineering, Finance, and Science
Designing analog circuits from performance specifications is a complex, multi-stage process encompassing topology selection, parameter inference, and layout feasibility. We introduce FALCON, a unified machine learning framework that enables fully automated, specification-driven analog circuit synthesis through topology selection and layout-constrained optimization. Given a target performance, FALCON first selects an appropriate circuit topology using a performance-driven classifier guided by human design heuristics. Next, it employs a custom, edge-centric graph neural network trained to map circuit topology and parameters to performance, enabling gradient-based parameter inference through the learned forward model. This inference is guided by a differentiable layout cost, derived from analytical equations capturing parasitic and frequency-dependent effects, and constrained by design rules. We train and evaluate FALCON on a large-scale custom dataset of 1M analog mm-wave circuits, generated and simulated using Cadence Spectre across 20 expert-designed topologies. Through this evaluation, FALCON demonstrates >99% accuracy in topology inference, <10% relative error in performance prediction, and efficient layout-aware design that completes in under 1 second per instance. Together, these results position FALCON as a practical and extensible foundation model for end-to-end analog circuit design automation.
title FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design
topic Machine Learning
Artificial Intelligence
Hardware Architecture
Computational Engineering, Finance, and Science
url https://arxiv.org/abs/2505.21923