Cover Image

iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Li, Runkai, Xiong, Jia, Wang, Xi
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Artificial Intelligence
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

MetaDSE: A Few-shot Meta-learning Framework for Cross-workload CPU Design Space Exploration
by: Xue, Runzhen, et al.
Published: (2025)

LLM-DSE: Searching Accelerator Parameters with LLM Agents
by: Wang, Hanyu, et al.
Published: (2025)

ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
by: Li, Runkai, et al.
Published: (2025)

Are LLMs Any Good for High-Level Synthesis?
by: Liao, Yuchao, et al.
Published: (2024)

Intelligent4DSE: Optimizing High-Level Synthesis Design Space Exploration with Graph Neural Networks and Large Language Models
by: Xu, Lei, et al.
Published: (2025)

Efficient Task Transfer for HLS DSE
by: Ding, Zijian, et al.
Published: (2024)

HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks
by: Abi-Karam, Stefan, et al.
Published: (2025)

FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
by: Abi-Karam, Stefan, et al.
Published: (2025)

Comprehensive Design Space Exploration for Tensorized Neural Network Hardware Accelerators
by: Zhang, Jinsong, et al.
Published: (2025)

Learning to Compare Hardware Designs for High-Level Synthesis
by: Bai, Yunsheng, et al.
Published: (2024)

ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
by: Fu, Lik Tung, et al.
Published: (2026)

SoberDSE: Sample-Efficient Design Space Exploration via Learning-Based Algorithm Selection
by: Xu, Lei, et al.
Published: (2026)

LLM-Driven Design Space Exploration of FPGA-based Accelerators
by: Sharma, Vinamra, et al.
Published: (2026)

ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesis
by: Peng, Zedong, et al.
Published: (2025)

OneDSE: A Unified Microprocessor Metric Prediction and Design Space Exploration Framework
by: Raj, Ritik, et al.
Published: (2025)

AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs
by: Ahmed, Md Rubel, et al.
Published: (2024)

NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI
by: Yang, Kaiyuan, et al.
Published: (2025)

System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints
by: Liao, Yuchao, et al.
Published: (2024)

LUMINA: LLM-Guided GPU Architecture Exploration via Bottleneck Analysis
by: Zhang, Tao, et al.
Published: (2026)

Agentic Architect: An Agentic AI Framework for Architecture Design Exploration and Optimization
by: Blasberg, Alexander, et al.
Published: (2026)

Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis
by: Qin, Zongyue, et al.
Published: (2024)

Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis
by: Li, Weikai, et al.
Published: (2024)

Classification-Based Automatic HDL Code Generation Using LLMs
by: Sun, Wenhao, et al.
Published: (2024)

CktEvo: Repository-Level RTL Code Benchmark for Design Evolution
by: Shi, Zhengyuan, et al.
Published: (2026)

ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
by: Zhang, Qijun, et al.
Published: (2025)

HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
by: Meng, Chang-Chih, et al.
Published: (2026)

Declarative Synthesis and Multi-Objective Optimization of Stripboard Circuit Layouts Using Answer Set Programming
by: Li, Fang
Published: (2025)

Multi-objective Optimization in CPU Design Space Exploration: Attention is All You Need
by: Xue, Runzhen, et al.
Published: (2024)

IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA
by: Jiang, Zesong, et al.
Published: (2024)

TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations
by: Wang, Dengfeng, et al.
Published: (2023)

DPUV4E: High-Throughput DPU Architecture Design for CNN on Versal ACAP
by: Li, Guoyu, et al.
Published: (2025)

GENIAL: Generative Design Space Exploration via Network Inversion for Low Power Algorithmic Logic Units
by: Bouvier, Maxence, et al.
Published: (2025)

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
by: Hemadri, Raghu Vamshi, et al.
Published: (2025)

Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning
by: Liao, Yuchao, et al.
Published: (2024)

ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications
by: Xing, Changwen, et al.
Published: (2025)

PIM-LLM: A High-Throughput Hybrid PIM Architecture for 1-bit LLMs
by: Malekar, Jinendra, et al.
Published: (2025)

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting
by: Shahidzadeh, Mohammad, et al.
Published: (2024)

HLSTransform: Energy-Efficient Llama 2 Inference on FPGAs Via High Level Synthesis
by: He, Andy, et al.
Published: (2024)

Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
by: Gao, Mingzhe, et al.
Published: (2024)

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs
by: Dang, Peng, et al.
Published: (2024)