Energy-Oriented Computing Architecture Simulator for SNN Training
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arXiv
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| Autores principales: | , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2025
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| Materias: | |
| Acceso en línea: | |
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| _version_ | 1866918045935468544 |
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| author | Ma, Yunhao Jia, Wanyi Lin, Yanyu Lin, Wenjie Zhu, Xueke Zhou, Huihui An, Fengwei |
| author_facet | Ma, Yunhao Jia, Wanyi Lin, Yanyu Lin, Wenjie Zhu, Xueke Zhou, Huihui An, Fengwei |
| contents | With the growing demand for intelligent computing, neuromorphic computing, a paradigm that mimics the structure and functionality of the human brain, offers a promising approach to developing new high-efficiency intelligent computing systems. Spiking Neural Networks (SNNs), the foundation of neuromorphic computing, have garnered significant attention due to their unique potential in energy efficiency and biomimetic neural processing. However, current hardware development for efficient SNN training lags significantly. No systematic energy evaluation methods exist for SNN training tasks. Therefore, this paper proposes an Energy-Oriented Computing Architecture Simulator (EOCAS) for SNN training to identify the optimal architecture. EOCAS investigates the high sparsity of spike signals, unique hardware design representations, energy assessment, and computation patterns to support energy optimization in various architectures. Under the guidance of EOCAS, we implement the power-aimed optimal hardware architecture through Verilog HDL and achieve low energy consumption using Synopsys Design Compiler with TSMC-28nm technology library under typical parameters. Compared with several State-Of-The-Art (SOTA) DNN and SNN works, our hardware architecture outstands others in various criteria. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_24137 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Energy-Oriented Computing Architecture Simulator for SNN Training Ma, Yunhao Jia, Wanyi Lin, Yanyu Lin, Wenjie Zhu, Xueke Zhou, Huihui An, Fengwei Hardware Architecture With the growing demand for intelligent computing, neuromorphic computing, a paradigm that mimics the structure and functionality of the human brain, offers a promising approach to developing new high-efficiency intelligent computing systems. Spiking Neural Networks (SNNs), the foundation of neuromorphic computing, have garnered significant attention due to their unique potential in energy efficiency and biomimetic neural processing. However, current hardware development for efficient SNN training lags significantly. No systematic energy evaluation methods exist for SNN training tasks. Therefore, this paper proposes an Energy-Oriented Computing Architecture Simulator (EOCAS) for SNN training to identify the optimal architecture. EOCAS investigates the high sparsity of spike signals, unique hardware design representations, energy assessment, and computation patterns to support energy optimization in various architectures. Under the guidance of EOCAS, we implement the power-aimed optimal hardware architecture through Verilog HDL and achieve low energy consumption using Synopsys Design Compiler with TSMC-28nm technology library under typical parameters. Compared with several State-Of-The-Art (SOTA) DNN and SNN works, our hardware architecture outstands others in various criteria. |
| title | Energy-Oriented Computing Architecture Simulator for SNN Training |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2505.24137 |