QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation
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| Main Authors: | , , , , , , , , , , , , , , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866917287155466240 |
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| author | Zhu, Yaoyu Huang, Di Lyu, Hanqi Zhang, Xiaoyun Li, Chongxiao Shi, Wenxuan Wu, Yutong Mu, Jianan Wang, Jinghua Zhao, Yang Jin, Pengwei Cheng, Shuyao Liang, Shengwen Zhang, Xishan Zhang, Rui Du, Zidong Guo, Qi Hu, Xing Chen, Yunji |
| author_facet | Zhu, Yaoyu Huang, Di Lyu, Hanqi Zhang, Xiaoyun Li, Chongxiao Shi, Wenxuan Wu, Yutong Mu, Jianan Wang, Jinghua Zhao, Yang Jin, Pengwei Cheng, Shuyao Liang, Shengwen Zhang, Xishan Zhang, Rui Du, Zidong Guo, Qi Hu, Xing Chen, Yunji |
| contents | Large language models (LLMs) trained via reinforcement learning with verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit, automatable verification, such as software programming and mathematical problems. Extending RLVR to electronic design automation (EDA), especially automatically generating hardware description languages (HDLs) like Verilog from natural-language (NL) specifications, however, poses three key challenges: the lack of automated and accurate verification environments, the scarcity of high-quality NL-code pairs, and the prohibitive computation cost of RLVR. To this end, we introduce CodeV-R1, an RLVR framework for training Verilog generation LLMs. First, we develop a rule-based testbench generator that performs robust equivalence checking against golden references. Second, we propose a round-trip data synthesis method that pairs open-source Verilog snippets with LLM-generated NL descriptions, verifies code-NL-code consistency via the generated testbench, and filters out inequivalent examples to yield a high-quality dataset. Third, we employ a two-stage "distill-then-RL" training pipeline: distillation for the cold start of reasoning abilities, followed by adaptive DAPO, our novel RLVR algorithm that can reduce training cost by adaptively adjusting sampling rate. The resulting model, CodeV-R1-7B, achieves 68.6% and 72.9% pass@1 on VerilogEval v2 and RTLLM v1.1, respectively, surpassing prior state-of-the-art by 12~20%, while even exceeding the performance of 671B DeepSeek-R1 on RTLLM. We have released our model, training code, and dataset to facilitate research in EDA and LLM communities. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_24183 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation Zhu, Yaoyu Huang, Di Lyu, Hanqi Zhang, Xiaoyun Li, Chongxiao Shi, Wenxuan Wu, Yutong Mu, Jianan Wang, Jinghua Zhao, Yang Jin, Pengwei Cheng, Shuyao Liang, Shengwen Zhang, Xishan Zhang, Rui Du, Zidong Guo, Qi Hu, Xing Chen, Yunji Machine Learning Hardware Architecture Programming Languages Large language models (LLMs) trained via reinforcement learning with verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit, automatable verification, such as software programming and mathematical problems. Extending RLVR to electronic design automation (EDA), especially automatically generating hardware description languages (HDLs) like Verilog from natural-language (NL) specifications, however, poses three key challenges: the lack of automated and accurate verification environments, the scarcity of high-quality NL-code pairs, and the prohibitive computation cost of RLVR. To this end, we introduce CodeV-R1, an RLVR framework for training Verilog generation LLMs. First, we develop a rule-based testbench generator that performs robust equivalence checking against golden references. Second, we propose a round-trip data synthesis method that pairs open-source Verilog snippets with LLM-generated NL descriptions, verifies code-NL-code consistency via the generated testbench, and filters out inequivalent examples to yield a high-quality dataset. Third, we employ a two-stage "distill-then-RL" training pipeline: distillation for the cold start of reasoning abilities, followed by adaptive DAPO, our novel RLVR algorithm that can reduce training cost by adaptively adjusting sampling rate. The resulting model, CodeV-R1-7B, achieves 68.6% and 72.9% pass@1 on VerilogEval v2 and RTLLM v1.1, respectively, surpassing prior state-of-the-art by 12~20%, while even exceeding the performance of 671B DeepSeek-R1 on RTLLM. We have released our model, training code, and dataset to facilitate research in EDA and LLM communities. |
| title | QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation |
| topic | Machine Learning Hardware Architecture Programming Languages |
| url | https://arxiv.org/abs/2505.24183 |