Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
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arXiv
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| Main Authors: | , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866910977476263936 |
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| author | Roy, Prithwish Basu Saha, Akashdeep Alam, Manaar Knechtel, Johann Maniatakos, Michail Sinanoglu, Ozgur Karri, Ramesh |
| author_facet | Roy, Prithwish Basu Saha, Akashdeep Alam, Manaar Knechtel, Johann Maniatakos, Michail Sinanoglu, Ozgur Karri, Ramesh |
| contents | Automated Verilog code synthesis poses significant challenges and typically demands expert oversight. Traditional high-level synthesis (HLS) methods often fail to scale for real-world designs. While large language models (LLMs) have enhanced scalability, they often introduce syntactical and logical errors requiring extensive post-generation verification. Here, we introduce a novel conjunctive normal form (CNF)-guided synthesis methodology. The idea is to have an LLM generate CNF clauses, a format widely used for formal verification and synthesis validation in hardware design, but here it is used to formally describe the desired circuit functionality. These CNF specifications are then deterministically converted into Verilog, ensuring correctness by construction. Our approach fine-tunes an open-source and lightweight LLM, namely the CPU-deployable LLama-3.2-3B-Instruct model (parameters < 4B), on a dataset of standard RTL components. Experimental results demonstrate that our approach reliably produces functionally correct Verilog code on the first attempt, compared to other lightweight open-source SoTA works such as Verigen (2B parameters) and RTLCoder (4-bit quantized with around 7B parameters). We will release our method and data in full post peer-review. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_00005 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form Roy, Prithwish Basu Saha, Akashdeep Alam, Manaar Knechtel, Johann Maniatakos, Michail Sinanoglu, Ozgur Karri, Ramesh Hardware Architecture Automated Verilog code synthesis poses significant challenges and typically demands expert oversight. Traditional high-level synthesis (HLS) methods often fail to scale for real-world designs. While large language models (LLMs) have enhanced scalability, they often introduce syntactical and logical errors requiring extensive post-generation verification. Here, we introduce a novel conjunctive normal form (CNF)-guided synthesis methodology. The idea is to have an LLM generate CNF clauses, a format widely used for formal verification and synthesis validation in hardware design, but here it is used to formally describe the desired circuit functionality. These CNF specifications are then deterministically converted into Verilog, ensuring correctness by construction. Our approach fine-tunes an open-source and lightweight LLM, namely the CPU-deployable LLama-3.2-3B-Instruct model (parameters < 4B), on a dataset of standard RTL components. Experimental results demonstrate that our approach reliably produces functionally correct Verilog code on the first attempt, compared to other lightweight open-source SoTA works such as Verigen (2B parameters) and RTLCoder (4-bit quantized with around 7B parameters). We will release our method and data in full post peer-review. |
| title | Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2506.00005 |