AEQUAM: Accelerating Quantum Algorithm Validation through FPGA-Based Emulation
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arXiv
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| Auteurs principaux: | , , , |
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| Format: | Preprint |
| Publié: |
2025
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| _version_ | 1866913959544619008 |
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| author | Lagostina, Lorenzo Volpe, Deborah Zamboni, Maurizio Turvani, Giovanna |
| author_facet | Lagostina, Lorenzo Volpe, Deborah Zamboni, Maurizio Turvani, Giovanna |
| contents | This work presents AEQUAM (Area Efficient QUAntum eMulation), a toolchain that enables faster and more accessible quantum circuit verification. It consists of a compiler that translates OpenQASM 2.0 into RISC-like instructions, Cython software models for selecting number representations and simulating circuits, and a VHDL generator that produces RTL descriptions for FPGA-based hardware emulators. The architecture leverages a SIMD approach to parallelize computation and reduces complexity by exploiting the sparsity of quantum gate matrices. The VHDL generator allows customization of the number of emulated qubits and parallelization levels to meet user requirements. Synthesized on an Altera Cyclone 10LP FPGA with a 20-bit fixed-point representation and nearest-type approximation, the architecture demonstrates better scalability than other state-of-the-art emulators. Specifically, the emulator has been validated by exploiting the well consolidated benchmark of mqt bench framework. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_01029 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | AEQUAM: Accelerating Quantum Algorithm Validation through FPGA-Based Emulation Lagostina, Lorenzo Volpe, Deborah Zamboni, Maurizio Turvani, Giovanna Quantum Physics Systems and Control This work presents AEQUAM (Area Efficient QUAntum eMulation), a toolchain that enables faster and more accessible quantum circuit verification. It consists of a compiler that translates OpenQASM 2.0 into RISC-like instructions, Cython software models for selecting number representations and simulating circuits, and a VHDL generator that produces RTL descriptions for FPGA-based hardware emulators. The architecture leverages a SIMD approach to parallelize computation and reduces complexity by exploiting the sparsity of quantum gate matrices. The VHDL generator allows customization of the number of emulated qubits and parallelization levels to meet user requirements. Synthesized on an Altera Cyclone 10LP FPGA with a 20-bit fixed-point representation and nearest-type approximation, the architecture demonstrates better scalability than other state-of-the-art emulators. Specifically, the emulator has been validated by exploiting the well consolidated benchmark of mqt bench framework. |
| title | AEQUAM: Accelerating Quantum Algorithm Validation through FPGA-Based Emulation |
| topic | Quantum Physics Systems and Control |
| url | https://arxiv.org/abs/2506.01029 |