Cover Image

HEC: Equivalence Verification Checking for Code Transformation via Equality Saturation

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Yin, Jiaqi, Song, Zhan, Agostini, Nicolas Bohm, Tumeo, Antonino, Yu, Cunxi
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Programming Languages
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation
by: Yin, Jiaqi, et al.
Published: (2025)

AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators
by: Agostini, Nicolas Bohm, et al.
Published: (2023)

Scaling Program Synthesis Based Technology Mapping with Equality Saturation
by: Smith, Gus Henry, et al.
Published: (2024)

E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
by: Chen, Chen, et al.
Published: (2025)

E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis
by: Chen, Chen, et al.
Published: (2024)

SpecLoop: An Agentic RTL-to-Specification Framework with Formal Verification Feedback Loop
by: Chang, Fu-Chieh, et al.
Published: (2026)

Comparing Methods for the Cross-Level Verification of SystemC Peripherals with Symbolic Execution
by: Rudkowski, Karl Aaron, et al.
Published: (2025)

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
by: Zhao, Zhuorui, et al.
Published: (2025)

Revisit Choice Network for Synthesis and Technology Mapping
by: Chen, Chen, et al.
Published: (2025)

VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
by: Niu, Juxin, et al.
Published: (2025)

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper
by: Yu, Cunxi
Published: (2025)

HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers
by: Yang, Yiyao, et al.
Published: (2025)

e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving
by: Yin, Jiaqi, et al.
Published: (2025)

SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
by: Zhuang, Jinming, et al.
Published: (2024)

VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
by: Zhao, Jiayu, et al.
Published: (2025)

CellE: Automated Standard Cell Library Extension via Equality Saturation
by: Ren, Yi, et al.
Published: (2026)

WaveCert: Translation Validation for Asynchronous Dataflow Programs via Dynamic Fractional Permissions
by: Lin, Zhengyao, et al.
Published: (2023)

AutoVeriFix+: High-Correctness RTL Generation via Trace-Aware Causal Fix and Semantic Redundancy Pruning
by: Tan, Yan, et al.
Published: (2026)

RTL++: Graph-enhanced LLM for RTL Code Generation
by: Akyash, Mohammad, et al.
Published: (2025)

Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)
by: Xu, Siyi, et al.
Published: (2025)

Partial Cross-Compilation and Mixed Execution for Accelerating Dynamic Binary Translation
by: Gu, Yuhao, et al.
Published: (2025)

ACT: Automatically Generating Compiler Backends from Tensor Accelerator ISA Descriptions
by: Jain, Devansh, et al.
Published: (2025)

The Program Hypergraph: Multi-Way Relational Structure for Geometric Algebra, Spatial Compute, and Physics-Aware Compilation
by: Haynes, Houston
Published: (2026)

Register Aggregation for Hardware Decompilation
by: Rao, Varun, et al.
Published: (2024)

Relaxed exception semantics for Arm-A (extended version)
by: Simner, Ben, et al.
Published: (2024)

An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
by: Zhang, Weichuang, et al.
Published: (2024)

There and Back Again: A Netlist's Tale with Much Egraphin'
by: Smith, Gus Henry, et al.
Published: (2024)

Tywaves: A Typed Waveform Viewer for Chisel
by: Meloni, Raffaele, et al.
Published: (2024)

Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators
by: Tanaka, Izumi, et al.
Published: (2026)

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
by: Liu, Shang, et al.
Published: (2023)

From CISC to RISC: language-model guided assembly transpilation
by: Heakl, Ahmed, et al.
Published: (2024)

MINISA: Minimal Instruction Set Architecture for Next-gen Reconfigurable Inference Accelerator
by: Tong, Jianming, et al.
Published: (2026)

Generation of Compiler Backends from Formal Models of Hardware
by: Smith, Gus Henry
Published: (2024)

Parameterized Hardware Design with Latency-Abstract Interfaces
by: Nigam, Rachit, et al.
Published: (2024)

FPGA Technology Mapping Using Sketch-Guided Program Synthesis
by: Smith, Gus Henry, et al.
Published: (2024)

Optimizing High-Level Synthesis Designs with Retrieval-Augmented Large Language Models
by: Xu, Haocheng, et al.
Published: (2024)

NEURA: A Unified and Retargetable Compilation Framework for Coarse-Grained Reconfigurable Architectures
by: Li, Shangkun, et al.
Published: (2026)

QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation
by: Zhang, Yang, et al.
Published: (2025)

Securing Cryptographic Software via Typed Assembly Language (Extended Version)
by: Song, Shixin, et al.
Published: (2025)

QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation
by: Zhu, Yaoyu, et al.
Published: (2025)