Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing

Fuente: arXiv

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Bibliographic Details
Main Author:	Yadav, Priyanshu
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Artificial Intelligence Signal Processing C.1.3, B.5.2, I.5.1 C.1.3, B.5.2, I.5.1 C.1.3, B.5.2, I.5.1
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2506.06693