VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code

Fuente: arXiv

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Bibliographic Details
Main Authors:	Hemadri, Raghu Vamshi, Bhandari, Jitendra, Nakkab, Andre, Knechtel, Johann, Gopalan, Badri P, Narayanaswamy, Ramesh, Karri, Ramesh, Garg, Siddharth
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Artificial Intelligence
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2506.07239