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| Main Authors: | , |
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| Format: | Preprint |
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2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2506.07873 |
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| _version_ | 1866912420609392640 |
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| author | Acevedo, Javier Fitzek, Frank H. P. |
| author_facet | Acevedo, Javier Fitzek, Frank H. P. |
| contents | The evolution of 5G and the emergence of 6G wireless communication systems impose higher demands for computing capabilities and lower power consumption in the front-end and processing circuitry. Furthermore, the incorporation of Artificial Intelligence (AI)/Machine Learning (ML) in the Radio Access Network (RAN) introduces heightened computational needs and stringent low-latency requirements for both training and inference. The concept of a Base Station on Chip (BSoC) addresses those demands by consolidating of the signal processing, neural network computations and network management functions into a single chip. This new computing platform relies on a sophisticated hardware/software co-design to optimize performance, power efficiency, and scalability, enabling a compact, yet adaptable and intelligent base station solution for next-generation wireless networks. This research investigates the efficient implementation of conventional Channel Estimation (CE), massive Multiple Input Multiple Output (mMIMO), and beamforming kernels on a state-of-the-art RISC-V vector Digital Signal Processors (DSP) to capitalize on Data Level Parallelism (DLP). Moreover, it explores how RISC-V Vector Extensions (RVV) combined with custom instructions can effectively address the throughput and latency demands of LOW Physical Layer (PHY) kernels. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_07873 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Towards a Base-Station-on-Chip: RISC-V Hardware Acceleration for wireless communication Acevedo, Javier Fitzek, Frank H. P. Signal Processing The evolution of 5G and the emergence of 6G wireless communication systems impose higher demands for computing capabilities and lower power consumption in the front-end and processing circuitry. Furthermore, the incorporation of Artificial Intelligence (AI)/Machine Learning (ML) in the Radio Access Network (RAN) introduces heightened computational needs and stringent low-latency requirements for both training and inference. The concept of a Base Station on Chip (BSoC) addresses those demands by consolidating of the signal processing, neural network computations and network management functions into a single chip. This new computing platform relies on a sophisticated hardware/software co-design to optimize performance, power efficiency, and scalability, enabling a compact, yet adaptable and intelligent base station solution for next-generation wireless networks. This research investigates the efficient implementation of conventional Channel Estimation (CE), massive Multiple Input Multiple Output (mMIMO), and beamforming kernels on a state-of-the-art RISC-V vector Digital Signal Processors (DSP) to capitalize on Data Level Parallelism (DLP). Moreover, it explores how RISC-V Vector Extensions (RVV) combined with custom instructions can effectively address the throughput and latency demands of LOW Physical Layer (PHY) kernels. |
| title | Towards a Base-Station-on-Chip: RISC-V Hardware Acceleration for wireless communication |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2506.07873 |