ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols

Fuente: arXiv

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Bibliographic Details
Main Authors:	Sheth, Arnav, Sheth, Ivaxi, Fritz, Mario
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Artificial Intelligence Computation and Language
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2506.07945