POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration
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arXiv
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| Autores principales: | , |
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| Formato: | Preprint |
| Publicado: |
2025
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| _version_ | 1866913888082067456 |
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| author | Lokhande, Mukul Vishvakarma, Santosh Kumar |
| author_facet | Lokhande, Mukul Vishvakarma, Santosh Kumar |
| contents | The increasing complexity of AI models requires flexible hardware capable of supporting diverse precision formats, particularly for energy-constrained edge platforms. This work presents PARV-CE, a SIMD-enabled, multi-precision MAC engine that performs efficient multiply-accumulate operations using a unified data-path for 4/8/16-bit fixed-point, floating point, and posit formats. The architecture incorporates a layer adaptive precision strategy to align computational accuracy with workload sensitivity, optimizing both performance and energy usage. PARV-CE integrates quantization-aware execution with a reconfigurable SIMD pipeline, enabling high-throughput processing with minimal overhead through hardware-software co-design. The results demonstrate up to 2x improvement in PDP and 3x reduction in resource usage compared to SoTA designs, while retaining accuracy within 1.8% FP32 baseline. The architecture supports both on-device training and inference across a range of workloads, including DNNs, RNNs, RL, and Transformer models. The empirical analysis establish PARVCE incorporated POLARON as a scalable and energy-efficient solution for precision-adaptive AI acceleration at edge. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_08785 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration Lokhande, Mukul Vishvakarma, Santosh Kumar Hardware Architecture Artificial Intelligence Computational Complexity Image and Video Processing The increasing complexity of AI models requires flexible hardware capable of supporting diverse precision formats, particularly for energy-constrained edge platforms. This work presents PARV-CE, a SIMD-enabled, multi-precision MAC engine that performs efficient multiply-accumulate operations using a unified data-path for 4/8/16-bit fixed-point, floating point, and posit formats. The architecture incorporates a layer adaptive precision strategy to align computational accuracy with workload sensitivity, optimizing both performance and energy usage. PARV-CE integrates quantization-aware execution with a reconfigurable SIMD pipeline, enabling high-throughput processing with minimal overhead through hardware-software co-design. The results demonstrate up to 2x improvement in PDP and 3x reduction in resource usage compared to SoTA designs, while retaining accuracy within 1.8% FP32 baseline. The architecture supports both on-device training and inference across a range of workloads, including DNNs, RNNs, RL, and Transformer models. The empirical analysis establish PARVCE incorporated POLARON as a scalable and energy-efficient solution for precision-adaptive AI acceleration at edge. |
| title | POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration |
| topic | Hardware Architecture Artificial Intelligence Computational Complexity Image and Video Processing |
| url | https://arxiv.org/abs/2506.08785 |