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| Format: | Preprint |
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2025
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| Online Access: | https://arxiv.org/abs/2506.09356 |
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| _version_ | 1866909939268583424 |
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| author | Pandey, Nilesh Basu, Dipanjan Banerjee, Sanjay K. |
| author_facet | Pandey, Nilesh Basu, Dipanjan Banerjee, Sanjay K. |
| contents | This paper presents the design and benchmarking of cryogenic bulk-FETs using an experimentally calibrated TCAD framework that integrates 2-D electrostatics and interface-trap effects from $T = 2$ K to 300 K. For a 28-nm node device, carrier transport is predominantly ballistic at $T = 2$ K and becomes quasi-ballistic as temperature increases. At cryogenic temperatures, higher interface-trap densities increase the effective threshold voltage and suppress subthreshold conduction. However, when the ON-state bias is adjusted to account for the trap-induced $V_t$ shift, interface traps are found to \emph{worsen} $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ along with degrading the subthreshold swing (SS) and reducing mobility across all temperatures. The spatial standard deviation $σ$ of the trap distribution modulates these behaviors: highly localized traps ($σ\sim 1$--$2$ nm) exacerbate short-channel effects (SCEs), whereas broader, nearly uniform distributions ($σ\ge 50$ nm) elevate the entire barrier and suppress SCEs until saturation as $σ\to L_g$. The TCAD predictions closely match experimental data at 4.2 K, 77 K, and 300 K, providing design guidelines to optimize $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$, SS, mobility, and DIBL for cryogenic CMOS technology nodes. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_09356 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Engineering Cryogenic FETs: Addressing SCEs and Impact of Interface Traps Down to 2 K Temperature Pandey, Nilesh Basu, Dipanjan Banerjee, Sanjay K. Applied Physics This paper presents the design and benchmarking of cryogenic bulk-FETs using an experimentally calibrated TCAD framework that integrates 2-D electrostatics and interface-trap effects from $T = 2$ K to 300 K. For a 28-nm node device, carrier transport is predominantly ballistic at $T = 2$ K and becomes quasi-ballistic as temperature increases. At cryogenic temperatures, higher interface-trap densities increase the effective threshold voltage and suppress subthreshold conduction. However, when the ON-state bias is adjusted to account for the trap-induced $V_t$ shift, interface traps are found to \emph{worsen} $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ along with degrading the subthreshold swing (SS) and reducing mobility across all temperatures. The spatial standard deviation $σ$ of the trap distribution modulates these behaviors: highly localized traps ($σ\sim 1$--$2$ nm) exacerbate short-channel effects (SCEs), whereas broader, nearly uniform distributions ($σ\ge 50$ nm) elevate the entire barrier and suppress SCEs until saturation as $σ\to L_g$. The TCAD predictions closely match experimental data at 4.2 K, 77 K, and 300 K, providing design guidelines to optimize $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$, SS, mobility, and DIBL for cryogenic CMOS technology nodes. |
| title | Engineering Cryogenic FETs: Addressing SCEs and Impact of Interface Traps Down to 2 K Temperature |
| topic | Applied Physics |
| url | https://arxiv.org/abs/2506.09356 |