Synchronization for Fault-Tolerant Quantum Computers
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arXiv
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| Format: | Preprint |
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2025
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| _version_ | 1866909646781939712 |
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| author | Maurya, Satvik Tannu, Swamit |
| author_facet | Maurya, Satvik Tannu, Swamit |
| contents | Quantum Error Correction (QEC) codes store information reliably in logical qubits by encoding them in a larger number of less reliable qubits. The surface code, known for its high resilience to physical errors, is a leading candidate for fault-tolerant quantum computing (FTQC). Logical qubits encoded with the surface code can be in different phases of their syndrome generation cycle, thereby introducing desynchronization in the system. This can occur due to the production of non-Clifford states, dropouts due to fabrication defects, and the use of other QEC codes with the surface code to reduce resource requirements. Logical operations require the syndrome generation cycles of the logical qubits involved to be synchronized. This requires the leading qubit to pause or slow down its cycle, allowing more errors to accumulate before the next cycle, thereby increasing the risk of uncorrectable errors.
To synchronize the syndrome generation cycles of logical qubits, we define three policies - Passive, Active, and Hybrid. The Passive policy is the baseline, and the simplest, wherein the leading logical qubits idle until they are synchronized with the remaining logical qubits. On the other hand, the Active policy aims to slow the leading logical qubits down gradually, by inserting short idle periods before multiple code cycles. This approach reduces the logical error rate (LER) by up to 2.4x compared to the Passive policy. The Hybrid policy further reduces the LER by up to 3.4x by reducing the synchronization slack and running a few additional rounds of error correction. Furthermore, the reduction in the logical error rate with the proposed synchronization policies enables a speedup in decoding latency of up to 2.2x with a circuit-level noise model. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_10258 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Synchronization for Fault-Tolerant Quantum Computers Maurya, Satvik Tannu, Swamit Quantum Physics Hardware Architecture Quantum Error Correction (QEC) codes store information reliably in logical qubits by encoding them in a larger number of less reliable qubits. The surface code, known for its high resilience to physical errors, is a leading candidate for fault-tolerant quantum computing (FTQC). Logical qubits encoded with the surface code can be in different phases of their syndrome generation cycle, thereby introducing desynchronization in the system. This can occur due to the production of non-Clifford states, dropouts due to fabrication defects, and the use of other QEC codes with the surface code to reduce resource requirements. Logical operations require the syndrome generation cycles of the logical qubits involved to be synchronized. This requires the leading qubit to pause or slow down its cycle, allowing more errors to accumulate before the next cycle, thereby increasing the risk of uncorrectable errors. To synchronize the syndrome generation cycles of logical qubits, we define three policies - Passive, Active, and Hybrid. The Passive policy is the baseline, and the simplest, wherein the leading logical qubits idle until they are synchronized with the remaining logical qubits. On the other hand, the Active policy aims to slow the leading logical qubits down gradually, by inserting short idle periods before multiple code cycles. This approach reduces the logical error rate (LER) by up to 2.4x compared to the Passive policy. The Hybrid policy further reduces the LER by up to 3.4x by reducing the synchronization slack and running a few additional rounds of error correction. Furthermore, the reduction in the logical error rate with the proposed synchronization policies enables a speedup in decoding latency of up to 2.2x with a circuit-level noise model. |
| title | Synchronization for Fault-Tolerant Quantum Computers |
| topic | Quantum Physics Hardware Architecture |
| url | https://arxiv.org/abs/2506.10258 |