Mapping and Scheduling Spiking Neural Networks On Segmented Ladder Bus Architectures
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arXiv
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| Format: | Preprint |
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2025
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| author | Huynh, Phu Khanh Catthoor, Francky Das, Anup |
| author_facet | Huynh, Phu Khanh Catthoor, Francky Das, Anup |
| contents | Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. The communication patterns in such systems are inherently sparse, asynchronous, and localized due to the spiking nature of neural events, characterized by temporal sparsity with occasional bursts of traffic. These characteristics necessitate interconnects optimized for handling high-activity bursts while consuming minimal power during idle periods. Dynamic segmented bus has been proposed a promising interconnect for its simplicity, scalability and low power consumption. However, deploying spiking neural network applications on such buses presents challenges, including substantial inter-cluster traffic, which can lead to network congestion, spike loss, and unnecessary energy expenditure. In this paper, we propose a three-step process to deploy SNN applications on dynamic segmented buses aiming to reduce spike loss and conserve energy. Firstly, we formulate optimization heuristics to mitigate spike loss and energy consumption based on application connectivity. Secondly, we analyze the application traffic to determine spike schedules that minimize traffic flooding. Lastly, we propose a routing algorithm to minimize spike traffic path crossings. We evaluate our approach using a cycle-accurate network simulator. The simulation results show that our algorithms can eliminate spike loss while keeping energy consumption significantly lower compared to conventional NoCs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_11286 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Mapping and Scheduling Spiking Neural Networks On Segmented Ladder Bus Architectures Huynh, Phu Khanh Catthoor, Francky Das, Anup Neural and Evolutionary Computing Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. The communication patterns in such systems are inherently sparse, asynchronous, and localized due to the spiking nature of neural events, characterized by temporal sparsity with occasional bursts of traffic. These characteristics necessitate interconnects optimized for handling high-activity bursts while consuming minimal power during idle periods. Dynamic segmented bus has been proposed a promising interconnect for its simplicity, scalability and low power consumption. However, deploying spiking neural network applications on such buses presents challenges, including substantial inter-cluster traffic, which can lead to network congestion, spike loss, and unnecessary energy expenditure. In this paper, we propose a three-step process to deploy SNN applications on dynamic segmented buses aiming to reduce spike loss and conserve energy. Firstly, we formulate optimization heuristics to mitigate spike loss and energy consumption based on application connectivity. Secondly, we analyze the application traffic to determine spike schedules that minimize traffic flooding. Lastly, we propose a routing algorithm to minimize spike traffic path crossings. We evaluate our approach using a cycle-accurate network simulator. The simulation results show that our algorithms can eliminate spike loss while keeping energy consumption significantly lower compared to conventional NoCs. |
| title | Mapping and Scheduling Spiking Neural Networks On Segmented Ladder Bus Architectures |
| topic | Neural and Evolutionary Computing |
| url | https://arxiv.org/abs/2506.11286 |