FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks
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arXiv
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| Main Authors: | , , , , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866916795006320640 |
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| author | Leon, Vasileios Bezaitis, Charalampos Lentaris, George Soudris, Dimitrios Reisis, Dionysios Papatheofanous, Elissaios-Alexios Kyriakos, Angelos Dunne, Aubrey Samuelsson, Arne Steenari, David |
| author_facet | Leon, Vasileios Bezaitis, Charalampos Lentaris, George Soudris, Dimitrios Reisis, Dionysios Papatheofanous, Elissaios-Alexios Kyriakos, Angelos Dunne, Aubrey Samuelsson, Arne Steenari, David |
| contents | The advent of computationally demanding algorithms and high data rate instruments in new space applications pushes the space industry to explore disruptive solutions for on-board data processing. We examine heterogeneous computing architectures involving high-performance and low-power commercial SoCs. The current paper implements an FPGA with VPU co-processing architecture utilizing the CIF & LCD interfaces for I/O data transfers. A Kintex FPGA serves as our framing processor and heritage accelerator, while we offload novel DSP/AI functions to a Myriad2 VPU. We prototype our architecture in the lab to evaluate the interfaces, the FPGA resource utilization, the VPU computational throughput, as well as the entire data handling system's performance, via custom benchmarking. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_12968 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks Leon, Vasileios Bezaitis, Charalampos Lentaris, George Soudris, Dimitrios Reisis, Dionysios Papatheofanous, Elissaios-Alexios Kyriakos, Angelos Dunne, Aubrey Samuelsson, Arne Steenari, David Hardware Architecture The advent of computationally demanding algorithms and high data rate instruments in new space applications pushes the space industry to explore disruptive solutions for on-board data processing. We examine heterogeneous computing architectures involving high-performance and low-power commercial SoCs. The current paper implements an FPGA with VPU co-processing architecture utilizing the CIF & LCD interfaces for I/O data transfers. A Kintex FPGA serves as our framing processor and heritage accelerator, while we offload novel DSP/AI functions to a Myriad2 VPU. We prototype our architecture in the lab to evaluate the interfaces, the FPGA resource utilization, the VPU computational throughput, as well as the entire data handling system's performance, via custom benchmarking. |
| title | FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2506.12968 |