Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space
Fuente:
arXiv
Guardado en:
| Autores principales: | , , , , , , , |
|---|---|
| Formato: | Preprint |
| Publicado: |
2025
|
| Materias: | |
| Acceso en línea: | |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
| _version_ | 1866911007187664896 |
|---|---|
| author | Leon, Vasileios Papatheofanous, Elissaios Alexios Lentaris, George Bezaitis, Charalampos Mastorakis, Nikolaos Bampilis, Georgios Reisis, Dionysios Soudris, Dimitrios |
| author_facet | Leon, Vasileios Papatheofanous, Elissaios Alexios Lentaris, George Bezaitis, Charalampos Mastorakis, Nikolaos Bampilis, Georgios Reisis, Dionysios Soudris, Dimitrios |
| contents | The ever-increasing demand for computational power and I/O throughput in space applications is transforming the landscape of on-board computing. A variety of Commercial-Off-The-Shelf (COTS) accelerators emerges as an attractive solution for payload processing to outperform the traditional radiation-hardened devices. Towards increasing the reliability of such COTS accelerators, the current paper explores and evaluates fault-tolerance techniques for the Zynq FPGA and the Myriad VPU, which are two device families being integrated in industrial space avionics architectures/boards, such as Ubotica's CogniSat, Xiphos' Q7S, and Cobham Gaisler's GR-VPX-XCKU060. On the FPGA side, we combine techniques such as memory scrubbing, partial reconfiguration, triple modular redundancy, and watchdogs. On the VPU side, we detect and correct errors in the instruction and data memories, as well as we apply redundancy at processor level (SHAVE cores). When considering FPGA with VPU co-processing, we also develop a fault-tolerant interface between the two devices based on the CIF/LCD protocols and our custom CRC error-detecting code. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_12971 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space Leon, Vasileios Papatheofanous, Elissaios Alexios Lentaris, George Bezaitis, Charalampos Mastorakis, Nikolaos Bampilis, Georgios Reisis, Dionysios Soudris, Dimitrios Hardware Architecture The ever-increasing demand for computational power and I/O throughput in space applications is transforming the landscape of on-board computing. A variety of Commercial-Off-The-Shelf (COTS) accelerators emerges as an attractive solution for payload processing to outperform the traditional radiation-hardened devices. Towards increasing the reliability of such COTS accelerators, the current paper explores and evaluates fault-tolerance techniques for the Zynq FPGA and the Myriad VPU, which are two device families being integrated in industrial space avionics architectures/boards, such as Ubotica's CogniSat, Xiphos' Q7S, and Cobham Gaisler's GR-VPX-XCKU060. On the FPGA side, we combine techniques such as memory scrubbing, partial reconfiguration, triple modular redundancy, and watchdogs. On the VPU side, we detect and correct errors in the instruction and data memories, as well as we apply redundancy at processor level (SHAVE cores). When considering FPGA with VPU co-processing, we also develop a fault-tolerant interface between the two devices based on the CIF/LCD protocols and our custom CRC error-detecting code. |
| title | Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2506.12971 |