Reconfigurable Digital RRAM Logic Enables In-Situ Pruning and Learning for Edge AI
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2025
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| _version_ | 1866909650011553792 |
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| author | Wang, Songqi Zhang, Yue Chen, Jia Zhang, Xinyuan Li, Yi Lin, Ning He, Yangu Yang, Jichang Yu, Yingjie Li, Yi Wang, Zhongrui Qi, Xiaojuan Wang, Han |
| author_facet | Wang, Songqi Zhang, Yue Chen, Jia Zhang, Xinyuan Li, Yi Lin, Ning He, Yangu Yang, Jichang Yu, Yingjie Li, Yi Wang, Zhongrui Qi, Xiaojuan Wang, Han |
| contents | The human brain simultaneously optimizes synaptic weights and topology by growing, pruning, and strengthening synapses while performing all computation entirely in memory. In contrast, modern artificial-intelligence systems separate weight optimization from topology optimization and depend on energy-intensive von Neumann architectures. Here, we present a software-hardware co-design that bridges this gap. On the algorithmic side, we introduce a real-time dynamic weight-pruning strategy that monitors weight similarity during training and removes redundancies on the fly, reducing operations by 26.80% on MNIST and 59.94% on ModelNet10 without sacrificing accuracy (91.44% and 77.75%, respectively). On the hardware side, we fabricate a reconfigurable, fully digital compute-in-memory (CIM) chip based on 180 nm one-transistor-one-resistor (1T1R) RRAM arrays. Each array embeds flexible Boolean logic (NAND, AND, XOR, OR), enabling both convolution and similarity evaluation inside memory and eliminating all ADC/DAC overhead. The digital design achieves zero bit-error, reduces silicon area by 72.30% and overall energy by 57.26% compared to analogue RRAM CIM, and lowers energy by 75.61% and 86.53% on MNIST and ModelNet10, respectively, relative to an NVIDIA RTX 4090. Together, our co-design establishes a scalable brain-inspired paradigm for adaptive, energy-efficient edge intelligence in the future. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_13151 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Reconfigurable Digital RRAM Logic Enables In-Situ Pruning and Learning for Edge AI Wang, Songqi Zhang, Yue Chen, Jia Zhang, Xinyuan Li, Yi Lin, Ning He, Yangu Yang, Jichang Yu, Yingjie Li, Yi Wang, Zhongrui Qi, Xiaojuan Wang, Han Hardware Architecture The human brain simultaneously optimizes synaptic weights and topology by growing, pruning, and strengthening synapses while performing all computation entirely in memory. In contrast, modern artificial-intelligence systems separate weight optimization from topology optimization and depend on energy-intensive von Neumann architectures. Here, we present a software-hardware co-design that bridges this gap. On the algorithmic side, we introduce a real-time dynamic weight-pruning strategy that monitors weight similarity during training and removes redundancies on the fly, reducing operations by 26.80% on MNIST and 59.94% on ModelNet10 without sacrificing accuracy (91.44% and 77.75%, respectively). On the hardware side, we fabricate a reconfigurable, fully digital compute-in-memory (CIM) chip based on 180 nm one-transistor-one-resistor (1T1R) RRAM arrays. Each array embeds flexible Boolean logic (NAND, AND, XOR, OR), enabling both convolution and similarity evaluation inside memory and eliminating all ADC/DAC overhead. The digital design achieves zero bit-error, reduces silicon area by 72.30% and overall energy by 57.26% compared to analogue RRAM CIM, and lowers energy by 75.61% and 86.53% on MNIST and ModelNet10, respectively, relative to an NVIDIA RTX 4090. Together, our co-design establishes a scalable brain-inspired paradigm for adaptive, energy-efficient edge intelligence in the future. |
| title | Reconfigurable Digital RRAM Logic Enables In-Situ Pruning and Learning for Edge AI |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2506.13151 |