From Block to Byte: Transforming PCIe SSDs with CXL Memory Protocol and Instruction Annotation
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arXiv
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| Main Authors: | , , , , , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866909652597342208 |
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| author | Kwon, Miryeong Gouk, Donghyun Jang, Junhyeok Baek, Jinwoo You, Hyunwoo Ji, Sangyoon Jung, Hongjoo Moon, Junseok Kang, Seungkwan Lee, Seungjun Jung, Myoungsoo |
| author_facet | Kwon, Miryeong Gouk, Donghyun Jang, Junhyeok Baek, Jinwoo You, Hyunwoo Ji, Sangyoon Jung, Hongjoo Moon, Junseok Kang, Seungkwan Lee, Seungjun Jung, Myoungsoo |
| contents | This paper explores how Compute Express Link (CXL) can transform PCIe-based block storage into a scalable, byte-addressable working memory. We address the challenges of adapting block storage to CXL's memory-centric model by emphasizing cacheability as a key enabler and advocating for Type 3 endpoint devices, referred to as CXL-SSDs. To validate our approach, we prototype a CXL-SSD on a custom FPGA platform and propose annotation mechanisms, Determinism and Bufferability, to enhance performance while preserving data persistency. Our simulation-based evaluation demonstrates that CXL-SSD achieves 10.9x better performance than PCIe-based memory expanders and further reduces latency by 5.4x with annotation enhancements. In workloads with high locality, CXL-SSD approaches DRAM-like performance due to efficient on-chip caching. This work highlights the feasibility of integrating block storage into CXL's ecosystem and provides a foundation for future memory-storage convergence. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_15613 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | From Block to Byte: Transforming PCIe SSDs with CXL Memory Protocol and Instruction Annotation Kwon, Miryeong Gouk, Donghyun Jang, Junhyeok Baek, Jinwoo You, Hyunwoo Ji, Sangyoon Jung, Hongjoo Moon, Junseok Kang, Seungkwan Lee, Seungjun Jung, Myoungsoo Hardware Architecture This paper explores how Compute Express Link (CXL) can transform PCIe-based block storage into a scalable, byte-addressable working memory. We address the challenges of adapting block storage to CXL's memory-centric model by emphasizing cacheability as a key enabler and advocating for Type 3 endpoint devices, referred to as CXL-SSDs. To validate our approach, we prototype a CXL-SSD on a custom FPGA platform and propose annotation mechanisms, Determinism and Bufferability, to enhance performance while preserving data persistency. Our simulation-based evaluation demonstrates that CXL-SSD achieves 10.9x better performance than PCIe-based memory expanders and further reduces latency by 5.4x with annotation enhancements. In workloads with high locality, CXL-SSD approaches DRAM-like performance due to efficient on-chip caching. This work highlights the feasibility of integrating block storage into CXL's ecosystem and provides a foundation for future memory-storage convergence. |
| title | From Block to Byte: Transforming PCIe SSDs with CXL Memory Protocol and Instruction Annotation |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2506.15613 |