DeepRTL2: A Versatile Model for RTL-Related Tasks
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866908414532124672 |
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| author | Liu, Yi Zhang, Hongji Zhou, Yunhao Shi, Zhengyuan Xu, Changran Xu, Qiang |
| author_facet | Liu, Yi Zhang, Hongji Zhou, Yunhao Shi, Zhengyuan Xu, Changran Xu, Qiang |
| contents | The integration of large language models (LLMs) into electronic design automation (EDA) has significantly advanced the field, offering transformative benefits, particularly in register transfer level (RTL) code generation and understanding. While previous studies have demonstrated the efficacy of fine-tuning LLMs for these generation-based tasks, embedding-based tasks, which are equally critical to EDA workflows, have been largely overlooked. These tasks, including natural language code search, RTL code functionality equivalence checking, and performance prediction, are essential for accelerating and optimizing the hardware design process. To address this gap, we present DeepRTL2, a family of versatile LLMs that unifies both generation- and embedding-based tasks related to RTL. By simultaneously tackling a broad range of tasks, DeepRTL2 represents the first model to provide a comprehensive solution to the diverse challenges in EDA. Through extensive experiments, we show that DeepRTL2 achieves state-of-the-art performance across all evaluated tasks. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_15697 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | DeepRTL2: A Versatile Model for RTL-Related Tasks Liu, Yi Zhang, Hongji Zhou, Yunhao Shi, Zhengyuan Xu, Changran Xu, Qiang Hardware Architecture Computation and Language Machine Learning The integration of large language models (LLMs) into electronic design automation (EDA) has significantly advanced the field, offering transformative benefits, particularly in register transfer level (RTL) code generation and understanding. While previous studies have demonstrated the efficacy of fine-tuning LLMs for these generation-based tasks, embedding-based tasks, which are equally critical to EDA workflows, have been largely overlooked. These tasks, including natural language code search, RTL code functionality equivalence checking, and performance prediction, are essential for accelerating and optimizing the hardware design process. To address this gap, we present DeepRTL2, a family of versatile LLMs that unifies both generation- and embedding-based tasks related to RTL. By simultaneously tackling a broad range of tasks, DeepRTL2 represents the first model to provide a comprehensive solution to the diverse challenges in EDA. Through extensive experiments, we show that DeepRTL2 achieves state-of-the-art performance across all evaluated tasks. |
| title | DeepRTL2: A Versatile Model for RTL-Related Tasks |
| topic | Hardware Architecture Computation and Language Machine Learning |
| url | https://arxiv.org/abs/2506.15697 |