Profile-Guided Temporal Prefetching
Fuente:
arXiv
Saved in:
| Main Authors: | Li, Mengming, Zhang, Qijun, Gao, Yichuan, Fang, Wenji, Lu, Yao, Ren, Yongqing, Xie, Zhiyao |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
by: Li, Mengming, et al.
Published: (2025)
by: Li, Mengming, et al.
Published: (2025)
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
by: Li, Mengming, et al.
Published: (2024)
by: Li, Mengming, et al.
Published: (2024)
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
by: Zhang, Qijun, et al.
Published: (2025)
by: Zhang, Qijun, et al.
Published: (2025)
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)
by: Liu, Shang, et al.
Published: (2025)
FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
by: Zhang, Qijun, et al.
Published: (2024)
by: Zhang, Qijun, et al.
Published: (2024)
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework
by: Zhang, Qijun, et al.
Published: (2025)
by: Zhang, Qijun, et al.
Published: (2025)
ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
by: Li, Mengming, et al.
Published: (2026)
by: Li, Mengming, et al.
Published: (2026)
ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
by: Zhang, Qijun, et al.
Published: (2025)
by: Zhang, Qijun, et al.
Published: (2025)
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
by: Li, Wenkai, et al.
Published: (2025)
by: Li, Wenkai, et al.
Published: (2025)
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
by: Yan, Zhiyuan, et al.
Published: (2024)
by: Yan, Zhiyuan, et al.
Published: (2024)
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
by: Fang, Wenji, et al.
Published: (2024)
by: Fang, Wenji, et al.
Published: (2024)
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
by: Liu, Shang, et al.
Published: (2023)
by: Liu, Shang, et al.
Published: (2023)
Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations
by: Zhang, Qijun, et al.
Published: (2024)
by: Zhang, Qijun, et al.
Published: (2024)
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
by: Fang, Wenji, et al.
Published: (2024)
by: Fang, Wenji, et al.
Published: (2024)
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
by: Fang, Wenji, et al.
Published: (2025)
by: Fang, Wenji, et al.
Published: (2025)
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
by: Fang, Wenji, et al.
Published: (2025)
by: Fang, Wenji, et al.
Published: (2025)
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
by: Fang, Wenji, et al.
Published: (2025)
by: Fang, Wenji, et al.
Published: (2025)
A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
by: Fang, Wenji, et al.
Published: (2025)
by: Fang, Wenji, et al.
Published: (2025)
AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications
by: Wu, Yuchao, et al.
Published: (2026)
by: Wu, Yuchao, et al.
Published: (2026)
Gaze into the Pattern: Characterizing Spatial Patterns with Internal Temporal Correlations for Hardware Prefetching
by: Chen, Zixiao, et al.
Published: (2024)
by: Chen, Zixiao, et al.
Published: (2024)
Pickle Prefetcher: Programmable and Scalable Last-Level Cache Prefetcher
by: Nguyen, Hoa, et al.
Published: (2025)
by: Nguyen, Hoa, et al.
Published: (2025)
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
by: Fang, Wenji, et al.
Published: (2026)
by: Fang, Wenji, et al.
Published: (2026)
Triangel: A High-Performance, Accurate, Timely On-Chip Temporal Prefetcher
by: Ainsworth, Sam, et al.
Published: (2024)
by: Ainsworth, Sam, et al.
Published: (2024)
A Case for Kolmogorov-Arnold Networks in Prefetching: Towards Low-Latency, Generalizable ML-Based Prefetchers
by: Kulkarni, Dhruv, et al.
Published: (2025)
by: Kulkarni, Dhruv, et al.
Published: (2025)
Exploring DRAM Cache Prefetching for Pooled Memory
by: Tirumalasetty, Chandrahas, et al.
Published: (2024)
by: Tirumalasetty, Chandrahas, et al.
Published: (2024)
Agile TLB Prefetching and Prediction Replacement Policy
by: Mersha, Melkamu, et al.
Published: (2024)
by: Mersha, Melkamu, et al.
Published: (2024)
DEER: Deep Runahead for Instruction Prefetching on Modern Mobile Workloads
by: Vahdatniya, Parmida, et al.
Published: (2025)
by: Vahdatniya, Parmida, et al.
Published: (2025)
SPPAM: Signature Pattern Prediction and Access-Map Prefetcher
by: Merrell, Maccoy, et al.
Published: (2026)
by: Merrell, Maccoy, et al.
Published: (2026)
ORAP: Optimized Row Access Prefetching for Rowhammer-mitigated Memory
by: Merrell, Maccoy, et al.
Published: (2026)
by: Merrell, Maccoy, et al.
Published: (2026)
PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender
by: Li, Luyi, et al.
Published: (2023)
by: Li, Luyi, et al.
Published: (2023)
PhantomFetch: Obfuscating Loads against Prefetcher Side-Channel Attacks
by: Zhang, Xingzhi, et al.
Published: (2025)
by: Zhang, Xingzhi, et al.
Published: (2025)
CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
by: Oh, Dongsuk, et al.
Published: (2025)
by: Oh, Dongsuk, et al.
Published: (2025)
TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
by: Tozlu, Yavuz Selim, et al.
Published: (2026)
by: Tozlu, Yavuz Selim, et al.
Published: (2026)
Enhancing Instruction Prefetching via Cache and TLB Management
by: Jamet, Alexandre Valentin, et al.
Published: (2026)
by: Jamet, Alexandre Valentin, et al.
Published: (2026)
PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching
by: Jiang, Fang, et al.
Published: (2024)
by: Jiang, Fang, et al.
Published: (2024)
WaSP: Warp Scheduling to Mimic Prefetching in Graphics Workloads
by: Joseph, Diya, et al.
Published: (2024)
by: Joseph, Diya, et al.
Published: (2024)
SLOFetch: Compressed-Hierarchical Instruction Prefetching for Cloud Microservices
by: Bao, Zerui, et al.
Published: (2025)
by: Bao, Zerui, et al.
Published: (2025)
CD-PIM: A High-Bandwidth and Compute-Efficient LPDDR5-Based PIM for Low-Batch LLM Acceleration on Edge-Device
by: Lin, Ye, et al.
Published: (2026)
by: Lin, Ye, et al.
Published: (2026)
A Joint Learning Approach to Hardware Caching and Prefetching
by: Yuan, Samuel, et al.
Published: (2025)
by: Yuan, Samuel, et al.
Published: (2025)
Understanding Simulated Architecture via gem5 Call-Stack Profiling
by: Söderström, Johan, et al.
Published: (2026)
by: Söderström, Johan, et al.
Published: (2026)
Similar Items
-
Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
by: Li, Mengming, et al.
Published: (2025) -
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
by: Li, Mengming, et al.
Published: (2024) -
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
by: Zhang, Qijun, et al.
Published: (2025) -
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025) -
FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
by: Zhang, Qijun, et al.
Published: (2024)