RCNet: $ΔΣ$ IADCs as Recurrent AutoEncoders
Fuente:
arXiv
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| Autori principali: | , , |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| _version_ | 1866918066119507968 |
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| author | Verdant, Arnaud Guicquero, William Chossat, Jérôme |
| author_facet | Verdant, Arnaud Guicquero, William Chossat, Jérôme |
| contents | This paper proposes a deep learning model (RCNet) for Delta-Sigma ($ΔΣ$) ADCs. Recurrent Neural Networks (RNNs) allow to describe both modulators and filters. This analogy is applied to Incremental ADCs (IADC). High-end optimizers combined with full-custom losses are used to define additional hardware design constraints: quantized weights, signal saturation, temporal noise injection, devices area. Focusing on DC conversion, our early results demonstrate that $SNR$ defined as an Effective Number Of Bits (ENOB) can be optimized under a certain hardware mapping complexity. The proposed RCNet succeeded to provide design tradeoffs in terms of $SNR$ ($>$13bit) versus area constraints ($<$14pF total capacitor) at a given $OSR$ (80 samples). Interestingly, it appears that the best RCNet architectures do not necessarily rely on high-order modulators, leveraging additional topology exploration degrees of freedom. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_16903 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | RCNet: $ΔΣ$ IADCs as Recurrent AutoEncoders Verdant, Arnaud Guicquero, William Chossat, Jérôme Hardware Architecture Machine Learning This paper proposes a deep learning model (RCNet) for Delta-Sigma ($ΔΣ$) ADCs. Recurrent Neural Networks (RNNs) allow to describe both modulators and filters. This analogy is applied to Incremental ADCs (IADC). High-end optimizers combined with full-custom losses are used to define additional hardware design constraints: quantized weights, signal saturation, temporal noise injection, devices area. Focusing on DC conversion, our early results demonstrate that $SNR$ defined as an Effective Number Of Bits (ENOB) can be optimized under a certain hardware mapping complexity. The proposed RCNet succeeded to provide design tradeoffs in terms of $SNR$ ($>$13bit) versus area constraints ($<$14pF total capacitor) at a given $OSR$ (80 samples). Interestingly, it appears that the best RCNet architectures do not necessarily rely on high-order modulators, leveraging additional topology exploration degrees of freedom. |
| title | RCNet: $ΔΣ$ IADCs as Recurrent AutoEncoders |
| topic | Hardware Architecture Machine Learning |
| url | https://arxiv.org/abs/2506.16903 |