Saved in:
| Main Author: | Wang, Shuangbao Paul |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2506.18780 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design
by: Ye, Haojie, et al.
Published: (2024)
by: Ye, Haojie, et al.
Published: (2024)
Security Properties for Open-Source Hardware Designs
by: Rogers, Jayden, et al.
Published: (2024)
by: Rogers, Jayden, et al.
Published: (2024)
The Quest to Build Trust Earlier in Digital Design
by: Tan, Benjamin
Published: (2024)
by: Tan, Benjamin
Published: (2024)
Taiyi: A high-performance CKKS accelerator for Practical Fully Homomorphic Encryption
by: Fan, Shengyu, et al.
Published: (2024)
by: Fan, Shengyu, et al.
Published: (2024)
Fastrack: Fast IO for Secure ML using GPU TEEs
by: Wang, Yongqin, et al.
Published: (2024)
by: Wang, Yongqin, et al.
Published: (2024)
Automated Physical Design Watermarking Leveraging Graph Neural Networks
by: Zhang, Ruisi, et al.
Published: (2024)
by: Zhang, Ruisi, et al.
Published: (2024)
Systematic Evaluation of Randomized Cache Designs against Cache Occupancy
by: Chakraborty, Anirban, et al.
Published: (2023)
by: Chakraborty, Anirban, et al.
Published: (2023)
AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures
by: Fu, Bo, et al.
Published: (2025)
by: Fu, Bo, et al.
Published: (2025)
ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips
by: Sheikh, Ahmad T., et al.
Published: (2024)
by: Sheikh, Ahmad T., et al.
Published: (2024)
@NTT: Algorithm-Targeted NTT hardware acceleration via Design-Time Constant Optimization
by: Nabeel, Mohammed, et al.
Published: (2026)
by: Nabeel, Mohammed, et al.
Published: (2026)
ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection
by: Zhang, Ruisi, et al.
Published: (2024)
by: Zhang, Ruisi, et al.
Published: (2024)
ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM
by: Ku, Jonathan, et al.
Published: (2024)
by: Ku, Jonathan, et al.
Published: (2024)
QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL
by: Reimann, Lennart M., et al.
Published: (2024)
by: Reimann, Lennart M., et al.
Published: (2024)
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture
by: Baidya, Paresh, et al.
Published: (2022)
by: Baidya, Paresh, et al.
Published: (2022)
Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms
by: Paul, Rourab, et al.
Published: (2026)
by: Paul, Rourab, et al.
Published: (2026)
Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study
by: Imtiaz, Sharjeel, et al.
Published: (2025)
by: Imtiaz, Sharjeel, et al.
Published: (2025)
Designing Secure Interconnects for Modern Microelectronics: From SoCs to Emerging Chiplet-Based Architectures
by: Halder, Dipal
Published: (2023)
by: Halder, Dipal
Published: (2023)
eFPE: Design, Implementation, and Evaluation of a Lightweight Format-Preserving Encryption Algorithm for Embedded Systems
by: Hegde, Nishant Vasantkumar, et al.
Published: (2025)
by: Hegde, Nishant Vasantkumar, et al.
Published: (2025)
Error Detection Schemes for Barrett Reduction of CT-BU on FPGA in Post Quantum Cryptography
by: Baidya, Paresh, et al.
Published: (2025)
by: Baidya, Paresh, et al.
Published: (2025)
Toleo: Scaling Freshness to Tera-scale Memory using CXL and PIM
by: Dong, Juechu, et al.
Published: (2024)
by: Dong, Juechu, et al.
Published: (2024)
Targeted Wearout Attacks in Microprocessor Cores
by: Mashburn, Joshua, et al.
Published: (2025)
by: Mashburn, Joshua, et al.
Published: (2025)
PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips
by: Yuksel, Ismail Emir, et al.
Published: (2025)
by: Yuksel, Ismail Emir, et al.
Published: (2025)
BackCache: Mitigating Contention-Based Cache Timing Attacks by Hiding Cache Line Evictions
by: Wang, Quancheng, et al.
Published: (2023)
by: Wang, Quancheng, et al.
Published: (2023)
Confidential Computing on Heterogeneous CPU-GPU Systems: Survey and Future Directions
by: Wang, Qifan, et al.
Published: (2024)
by: Wang, Qifan, et al.
Published: (2024)
BOLT: Bandwidth-Optimized Lightning-Fast Oblivious Map powered by Secure HBM Accelerators
by: Guo, Yitong, et al.
Published: (2025)
by: Guo, Yitong, et al.
Published: (2025)
Teapot: Efficiently Uncovering Spectre Gadgets in COTS Binaries
by: Lin, Fangzheng, et al.
Published: (2024)
by: Lin, Fangzheng, et al.
Published: (2024)
Older and Wiser: The Marriage of Device Aging and Intellectual Property Protection of Deep Neural Networks
by: Lin, Ning, et al.
Published: (2024)
by: Lin, Ning, et al.
Published: (2024)
The Road to Trust: Building Enclaves within Confidential VMs
by: Wang, Wenhao, et al.
Published: (2024)
by: Wang, Wenhao, et al.
Published: (2024)
Dishonest Approximate Computing: A Coming Crisis for Cloud Clients
by: Wang, Ye, et al.
Published: (2024)
by: Wang, Ye, et al.
Published: (2024)
High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography
by: Tan, Weihang, et al.
Published: (2021)
by: Tan, Weihang, et al.
Published: (2021)
CipherGuard: Compiler-aided Mitigation against Ciphertext Side-channel Attacks
by: Jiang, Ke, et al.
Published: (2025)
by: Jiang, Ke, et al.
Published: (2025)
LaMoS: Enabling Efficient Large Number Modular Multiplication through SRAM-based CiM Acceleration
by: Li, Haomin, et al.
Published: (2025)
by: Li, Haomin, et al.
Published: (2025)
Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking
by: Li, Weihang, et al.
Published: (2025)
by: Li, Weihang, et al.
Published: (2025)
PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption
by: Tan, Weihang, et al.
Published: (2023)
by: Tan, Weihang, et al.
Published: (2023)
Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V
by: Bolat, Alperen, et al.
Published: (2025)
by: Bolat, Alperen, et al.
Published: (2025)
CIBPU: A Conflict-Invisible Secure Branch Prediction Unit
by: Zhou, Zhe, et al.
Published: (2025)
by: Zhou, Zhe, et al.
Published: (2025)
PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching
by: Jiang, Fang, et al.
Published: (2024)
by: Jiang, Fang, et al.
Published: (2024)
DASICS White Paper: Enhancing Memory Protection with Dynamic Compartmentalization
by: Jin, Yue, et al.
Published: (2023)
by: Jin, Yue, et al.
Published: (2023)
ALLMod: Exploring $\underline{\mathbf{A}}$rea-Efficiency of $\underline{\mathbf{L}}$UT-based $\underline{\mathbf{L}}$arge Number $\underline{\mathbf{Mod}}$ular Reduction via Hybrid Workloads
by: Liu, Fangxin, et al.
Published: (2025)
by: Liu, Fangxin, et al.
Published: (2025)
A High Performance and Efficient Post-Quantum Crypto-Processor for FrodoKEM
by: Li, Kai, et al.
Published: (2026)
by: Li, Kai, et al.
Published: (2026)
Similar Items
-
Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design
by: Ye, Haojie, et al.
Published: (2024) -
Security Properties for Open-Source Hardware Designs
by: Rogers, Jayden, et al.
Published: (2024) -
The Quest to Build Trust Earlier in Digital Design
by: Tan, Benjamin
Published: (2024) -
Taiyi: A high-performance CKKS accelerator for Practical Fully Homomorphic Encryption
by: Fan, Shengyu, et al.
Published: (2024) -
Fastrack: Fast IO for Secure ML using GPU TEEs
by: Wang, Yongqin, et al.
Published: (2024)