OptGM: An Optimized Gate Merging Method to Mitigate NBTI in Digital Circuits
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arXiv
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| Format: | Preprint |
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2025
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| _version_ | 1866909946617004032 |
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| author | Hajisadeghi, Amir M. Ghane, Maryam Zarandi, Hamid R. |
| author_facet | Hajisadeghi, Amir M. Ghane, Maryam Zarandi, Hamid R. |
| contents | This paper presents OptGM, an optimized gate merging method designed to mitigate negative bias temperature instability (NBTI) in digital circuits. First, the proposed approach effectively identifies NBTI-critical internal nodes, defined as those with a signal probability exceeding a predefined threshold. Next, based on the proposed optimized algorithm, the sensitizer gate (which drives the critical node) and the sensitive gate (which is fed by it) are merged into a new complex gate. This complex gate preserves the original logic while eliminating NBTI-critical nodes. Finally, to evaluate the effectiveness of OptGM, we assess it on several combinational and sequential benchmark circuits. Simulation results demonstrate that, on average, the number of NBTI-critical transistors (i.e., PMOS transistors connected to critical nodes), NBTI-induced delay degradation, and the total transistor count are reduced by 89.29%, 23.87%, and 6.47%, respectively. Furthermore, OptGM enhances performance per cost (PPC) by 12.8% on average, with minimal area overhead. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_21487 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | OptGM: An Optimized Gate Merging Method to Mitigate NBTI in Digital Circuits Hajisadeghi, Amir M. Ghane, Maryam Zarandi, Hamid R. Hardware Architecture This paper presents OptGM, an optimized gate merging method designed to mitigate negative bias temperature instability (NBTI) in digital circuits. First, the proposed approach effectively identifies NBTI-critical internal nodes, defined as those with a signal probability exceeding a predefined threshold. Next, based on the proposed optimized algorithm, the sensitizer gate (which drives the critical node) and the sensitive gate (which is fed by it) are merged into a new complex gate. This complex gate preserves the original logic while eliminating NBTI-critical nodes. Finally, to evaluate the effectiveness of OptGM, we assess it on several combinational and sequential benchmark circuits. Simulation results demonstrate that, on average, the number of NBTI-critical transistors (i.e., PMOS transistors connected to critical nodes), NBTI-induced delay degradation, and the total transistor count are reduced by 89.29%, 23.87%, and 6.47%, respectively. Furthermore, OptGM enhances performance per cost (PPC) by 12.8% on average, with minimal area overhead. |
| title | OptGM: An Optimized Gate Merging Method to Mitigate NBTI in Digital Circuits |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2506.21487 |