Cover Image

FloorPlan-DeepSeek (FPDS): A multimodal approach to floorplan generation using vector-based next room prediction

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Yin, Jun, Zeng, Pengyu, Zhong, Jing, Li, Peilin, Zhang, Miao, Luo, Ran, Lu, Shuai
Format:	Preprint
Published:	2025
Subjects:	Computation and Language Artificial Intelligence Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Hardware-Centric Analysis of DeepSeek's Multi-Head Latent Attention
by: Geens, Robin, et al.
Published: (2025)

Versatile silicon integrated photonic processor: a reconfigurable solution for next-generation AI clusters
by: Zhu, Ying, et al.
Published: (2025)

Optimizing and Exploring System Performance in Compact Processing-in-Memory-based Chips
by: Chen, Peilin, et al.
Published: (2025)

Titanus: Enabling KV Cache Pruning and Quantization On-the-Fly for LLM Acceleration
by: Chen, Peilin, et al.
Published: (2025)

Emerging memory technologies at room/cryogenic temperature
by: Raman, Siddhartha Raman Sundara
Published: (2026)

Insights into DeepSeek-V3: Scaling Challenges and Reflections on Hardware for AI Architectures
by: Zhao, Chenggang, et al.
Published: (2025)

Theoretical complexity analysis of many-cores on a single chip
by: Ginosar, Ran
Published: (2025)

Addressing memory bandwidth scalability in vector processors for streaming applications
by: Altayo, Jordi, et al.
Published: (2025)

RISC-V V Vector Extension (RVV) with reduced number of vector registers
by: Jacobs, Eino, et al.
Published: (2024)

DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing
by: Zhang, Yuhan, et al.
Published: (2026)

MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
by: You, Dean, et al.
Published: (2025)

Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
by: Sehm, Robin, et al.
Published: (2025)

Python-based DSL for generating Verilog model of Synchronous Digital Circuits
by: Datar, Mandar, et al.
Published: (2024)

3D Stack In-Sensor-Computing (3DS-ISC): Accelerating Time-Surface Construction for Neuromorphic Event Cameras
by: Shang, Hongyang, et al.
Published: (2025)

The Bicameral Cache: a split cache for vector architectures
by: Rebolledo, Susana, et al.
Published: (2024)

LEXI: Lossless Exponent Coding for Efficient Inter-Chiplet Communication in Hybrid LLMs
by: Sun, Miao, et al.
Published: (2026)

End-to-End Transformer Acceleration Through Processing-in-Memory Architectures
by: Yang, Xiaoxuan, et al.
Published: (2025)

A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator
by: Yang, Junyi, et al.
Published: (2026)

CADC: Crossbar-Aware Dendritic Convolution for Efficient In-memory Computing
by: Dong, Shuai, et al.
Published: (2025)

Near-Memory Architecture for Threshold-Ordinal Surface-Based Corner Detection of Event Cameras
by: Shang, Hongyang, et al.
Published: (2025)

MemIntelli: A Generic End-to-End Simulation Framework for Memristive Intelligent Computing
by: Zhou, Houji, et al.
Published: (2025)

LarQucut: A New Cutting and Mapping Approach for Large-sized Quantum Circuits in Distributed Quantum Computing (DQC) Environments
by: Dou, Xinglei, et al.
Published: (2025)

Performance Analysis of Matrix Multiplication for Deep Learning on the Edge
by: Ramírez, Cristian, et al.
Published: (2024)

A Novel Cost-Effective MIMO Architecture with Ray Antenna Array for Enhanced Wireless Communication Performance
by: Dong, Zhenjun, et al.
Published: (2025)

SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm
by: Liu, Meng, et al.
Published: (2024)

In-Memory ADC-Based Nonlinear Activation Quantization for Efficient In-Memory Computing
by: Dong, Shuai, et al.
Published: (2026)

PacQ: A SIMT Microarchitecture for Efficient Dataflow in Hyper-asymmetric GEMMs
by: Yin, Ruokai, et al.
Published: (2025)

A high-level synthesis approach for precisely-timed, energy-efficient embedded systems
by: Liao, Yuchao, et al.
Published: (2024)

From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
by: Zhang, Jie, et al.
Published: (2026)

Polaris: Multi-Fidelity Design Space Exploration of Deep Learning Accelerators
by: Sakhuja, Chirag, et al.
Published: (2024)

SigDLA: A Deep Learning Accelerator Extension for Signal Processing
by: Fu, Fangfa, et al.
Published: (2024)

A Survey on LUT-based Deep Neural Networks Implemented in FPGAs
by: Guo, Zeyu
Published: (2025)

A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges
by: Zhong, Xinchao, et al.
Published: (2024)

A Sparsity-Aware Autonomous Path Planning Accelerator with HW/SW Co-Design and Multi-Level Dataflow Optimization
by: Zhang, Yifan, et al.
Published: (2025)

A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)

HFRWKV: A High-Performance Fully On-Chip Hardware Accelerator for RWKV
by: Shijie, Liu, et al.
Published: (2026)

Field-Programmable Gate Array Architecture for Deep Learning: Survey & Future Directions
by: Boutros, Andrew, et al.
Published: (2024)

A Low-Power Sparse Deep Learning Accelerator with Optimized Data Reuse
by: Hsu, Kai-Chieh, et al.
Published: (2025)

Systolic Array Data Flows for Efficient Matrix Multiplication in Deep Neural Networks
by: Raja, Tejas
Published: (2024)

StruM: Structured Mixed Precision for Efficient Deep Learning Hardware Codesign
by: Wu, Michael, et al.
Published: (2025)