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| Format: | Preprint |
| Veröffentlicht: |
2025
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| Online-Zugang: | https://arxiv.org/abs/2506.22107 |
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| _version_ | 1866918072900648960 |
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| author | Jalilvand, Amir Hossein Najafi, M. Hassan |
| author_facet | Jalilvand, Amir Hossein Najafi, M. Hassan |
| contents | Sorting is a fundamental operation in computer systems and is widely used in applications such as databases, data analytics, and hardware accelerators. Unary computing has recently emerged as a low-cost and power-efficient paradigm for implementing hardware sorters by eliminating the need for complex arithmetic operations. However, existing comparison-free unary computing-based designs suffer from significant area and power overhead due to costly unary number generators.
In this paper, we present a novel ascending-order unary sorting module featuring a finite-state-machine-based unary number generator that significantly reduces implementation costs. By generating right-aligned unary streams using a two-state finite-state machine, our architecture iteratively identifies the minimum input value in each cycle without conventional comparators. Synthesis results in a 45nm technology node demonstrate up to 82% reduction in area and 70% reduction in power consumption compared to state-of-the-art unary designs. The proposed sorter offers a promising solution for energy-constrained and resource-limited hardware systems. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2506_22107 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Power- and Area-Efficient Unary Sorting Architecture Using FSM-Based Unary Number Generator Jalilvand, Amir Hossein Najafi, M. Hassan Hardware Architecture Sorting is a fundamental operation in computer systems and is widely used in applications such as databases, data analytics, and hardware accelerators. Unary computing has recently emerged as a low-cost and power-efficient paradigm for implementing hardware sorters by eliminating the need for complex arithmetic operations. However, existing comparison-free unary computing-based designs suffer from significant area and power overhead due to costly unary number generators. In this paper, we present a novel ascending-order unary sorting module featuring a finite-state-machine-based unary number generator that significantly reduces implementation costs. By generating right-aligned unary streams using a two-state finite-state machine, our architecture iteratively identifies the minimum input value in each cycle without conventional comparators. Synthesis results in a 45nm technology node demonstrate up to 82% reduction in area and 70% reduction in power consumption compared to state-of-the-art unary designs. The proposed sorter offers a promising solution for energy-constrained and resource-limited hardware systems. |
| title | Power- and Area-Efficient Unary Sorting Architecture Using FSM-Based Unary Number Generator |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2506.22107 |