ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
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arXiv
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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866908981414330368 |
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| author | Li, Runkai Xiong, Jia He, Xiuyuan Zhao, Jieru Lv, Jiaqi Fang, Haowen Qi, Lei Wang, Xi |
| author_facet | Li, Runkai Xiong, Jia He, Xiuyuan Zhao, Jieru Lv, Jiaqi Fang, Haowen Qi, Lei Wang, Xi |
| contents | High-Level Synthesis (HLS) improves IC development productivity by enabling hardware design from C-like languages. However, strict coding constraints and design-specific optimizations limit its widespread adoption. While recent efforts employ large language models (LLMs) to assist HLS design, they often struggle with synthesizability rules and directive semantics. To this end, we introduce ChatHLS, a multi-agent HLS design framework that leverages specialized LLMs for automated debugging and directive tuning. ChatHLS incorporates an adaptive error case expansion mechanism, combined with a reasoning-to-instruction analysis method to accurately diagnose HLS errors. To optimize hardware performance, it enables QoR-aware reasoning to learn the impact of HLS directives on the quality of results (QoR). Experimental results demonstrate that ChatHLS outperforms Gemini-3-pro with a 32.6% relative improvement in debugging, while achieving significant speedups across various HLS kernels and neural network accelerators. These results underscore the potential of ChatHLS for agile hardware development. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2507_00642 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis Li, Runkai Xiong, Jia He, Xiuyuan Zhao, Jieru Lv, Jiaqi Fang, Haowen Qi, Lei Wang, Xi Hardware Architecture High-Level Synthesis (HLS) improves IC development productivity by enabling hardware design from C-like languages. However, strict coding constraints and design-specific optimizations limit its widespread adoption. While recent efforts employ large language models (LLMs) to assist HLS design, they often struggle with synthesizability rules and directive semantics. To this end, we introduce ChatHLS, a multi-agent HLS design framework that leverages specialized LLMs for automated debugging and directive tuning. ChatHLS incorporates an adaptive error case expansion mechanism, combined with a reasoning-to-instruction analysis method to accurately diagnose HLS errors. To optimize hardware performance, it enables QoR-aware reasoning to learn the impact of HLS directives on the quality of results (QoR). Experimental results demonstrate that ChatHLS outperforms Gemini-3-pro with a 32.6% relative improvement in debugging, while achieving significant speedups across various HLS kernels and neural network accelerators. These results underscore the potential of ChatHLS for agile hardware development. |
| title | ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2507.00642 |