Cover Image

Hardware-Accelerated Algorithm for Complex Function Roots Density Graph Plotting

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Tang, Ruibai, Quan, Chengbin
Format:	Preprint
Published:	2025
Subjects:	Mathematical Software Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Inexactness and Correction of Floating-Point Reciprocal, Division and Square Root
by: Dutton, Lucas M., et al.
Published: (2024)

Generalized Methodology for Determining Numerical Features of Hardware Floating-Point Matrix Multipliers: Part I
by: Khattak, Faizan A, et al.
Published: (2025)

SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers
by: Scheffler, Paul, et al.
Published: (2024)

Accelerating Transistor-Level Simulation of Integrated Circuits via Equivalence of RC Long-Chain Structures
by: Tang, Ruibai, et al.
Published: (2025)

DGEMM without FP64 Arithmetic - Using FP64 Emulation and FP8 Tensor Cores with Ozaki Scheme
by: Mukunoki, Daichi
Published: (2025)

EquivFusion: Unifying Hardware Equivalence Checking from Algorithms to Netlists via MLIR
by: Zhu, Jiaying, et al.
Published: (2026)

Evaluation of POSIT Arithmetic with Accelerators
by: Nakasato, Naohito, et al.
Published: (2024)

Accurate Models of NVIDIA Tensor Cores
by: Khattak, Faizan A., et al.
Published: (2025)

A Hybrid Residue Floating Numerical Architecture for High Precision Arithmetic on FPGAs
by: Darvishi, Mostafa
Published: (2025)

MATLAB Simulator of Level-Index Arithmetic
by: Mikaitis, Mantas
Published: (2024)

Mixed-precision finite element kernels and assembly: Rounding error analysis and hardware acceleration
by: Croci, M., et al.
Published: (2024)

LeGend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
by: Miao, Mingkai, et al.
Published: (2026)

C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
by: Collini, Luca, et al.
Published: (2024)

Toward Capturing Genetic Epistasis From Multivariate Genome-Wide Association Studies Using Mixed-Precision Kernel Ridge Regression
by: Ltaief, Hatem, et al.
Published: (2024)

Fast and energy-efficient derivatives risk analysis: Streaming option Greeks on Xilinx and Intel FPGAs
by: Klaisoongnoen, Mark, et al.
Published: (2022)

DRCY: Agentic Hardware Design Reviews
by: Dumont, Kyle, et al.
Published: (2026)

FuzzWiz -- Fuzzing Framework for Efficient Hardware Coverage
by: Gadde, Deepak Narayan, et al.
Published: (2024)

The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages
by: Schreiner, Johannes, et al.
Published: (2024)

Hardware.jl - An MLIR-based Julia HLS Flow (Work in Progress)
by: Short, Benedict, et al.
Published: (2025)

ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development
by: Wang, Bowei, et al.
Published: (2025)

KernelCraft: Benchmarking for Agentic Close-to-Metal Kernel Generation on Emerging Hardware
by: Nie, Jiayi, et al.
Published: (2026)

Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
by: Gai, Jiahao, et al.
Published: (2025)

Is Agentic AI Ready for Real-World Hardware Engineering? A Deep Dive with Phoenix-bench
by: Zou, Qingyun, et al.
Published: (2026)

Selective Parallel Loading of Large-Scale Compressed Graphs with ParaGrapher
by: Esfahani, Mohsen Koohi, et al.
Published: (2024)

Understanding Accelerator Compilers via Performance Profiling
by: Yorihiro, Ayaka, et al.
Published: (2025)

Accelerating PageRank Algorithmic Tasks with a new Programmable Hardware Architecture
by: Chowdhury, Md Rownak Hossain, et al.
Published: (2024)

Fast Graph Vector Search via Hardware Acceleration and Delayed-Synchronization Traversal
by: Jiang, Wenqi, et al.
Published: (2024)

NX-CGRA: A Programmable Hardware Accelerator for Core Transformer Algorithms on Edge Devices
by: Prasad, Rohit
Published: (2025)

FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
by: Shih, Yu-An, et al.
Published: (2025)

Offloading Data Center Tax
by: Revankar, Akshay, et al.
Published: (2025)

A Vertically Integrated Framework for Templatized Chip Design
by: Kim, Jeongeun, et al.
Published: (2025)

Structural Mutation Based Differential Testing for FPGA Logic Synthesis Compilers
by: Xu, Zhihao, et al.
Published: (2025)

Scalable Software Testing in Fast Virtual Platforms: Leveraging SystemC, QEMU and Containerization
by: Jünger, Lukas, et al.
Published: (2025)

ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions
by: Vavelidou, Ioanna, et al.
Published: (2026)

Using LLMs to Facilitate Formal Verification of RTL
by: Orenes-Vera, Marcelo, et al.
Published: (2023)

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026)

MEIC: Re-thinking RTL Debug Automation using LLMs
by: Xu, Ke, et al.
Published: (2024)

AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs
by: Zhou, Xiaofeng, et al.
Published: (2026)

Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
by: Armato, Antonino, et al.
Published: (2026)

FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)