Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure
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arXiv
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| Autori principali: | , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| _version_ | 1866908516146479104 |
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| author | Xie, Rui Haq, Asad Ul Fang, Yunhua Ma, Linsen Sen, Sanchari Venkataramani, Swagath Liu, Liu Zhang, Tong |
| author_facet | Xie, Rui Haq, Asad Ul Fang, Yunhua Ma, Linsen Sen, Sanchari Venkataramani, Swagath Liu, Liu Zhang, Tong |
| contents | High-Bandwidth Memory (HBM) delivers exceptional bandwidth and energy efficiency for AI workloads, but its high cost per bit, driven in part by stringent on-die reliability requirements, poses a growing barrier to scalable deployment. This work explores a system-level approach to cost reduction by eliminating on-die ECC and shifting all fault management to the memory controller. We introduce a domain-specific ECC framework combining large-codeword Reed--Solomon~(RS) correction with lightweight fine-grained CRC detection, differential parity updates to mitigate write amplification, and tunable protection based on data importance. Our evaluation using LLM inference workloads shows that, even under raw HBM bit error rates up to $10^{-3}$, the system retains over 78\% of throughput and 97\% of model accuracy compared with systems equipped with ideal error-free HBM. By treating reliability as a tunable system parameter rather than a fixed hardware constraint, our design opens a new path toward low-cost, high-performance HBM deployment in AI infrastructure. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2507_02654 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure Xie, Rui Haq, Asad Ul Fang, Yunhua Ma, Linsen Sen, Sanchari Venkataramani, Swagath Liu, Liu Zhang, Tong Hardware Architecture High-Bandwidth Memory (HBM) delivers exceptional bandwidth and energy efficiency for AI workloads, but its high cost per bit, driven in part by stringent on-die reliability requirements, poses a growing barrier to scalable deployment. This work explores a system-level approach to cost reduction by eliminating on-die ECC and shifting all fault management to the memory controller. We introduce a domain-specific ECC framework combining large-codeword Reed--Solomon~(RS) correction with lightweight fine-grained CRC detection, differential parity updates to mitigate write amplification, and tunable protection based on data importance. Our evaluation using LLM inference workloads shows that, even under raw HBM bit error rates up to $10^{-3}$, the system retains over 78\% of throughput and 97\% of model accuracy compared with systems equipped with ideal error-free HBM. By treating reliability as a tunable system parameter rather than a fixed hardware constraint, our design opens a new path toward low-cost, high-performance HBM deployment in AI infrastructure. |
| title | Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2507.02654 |