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| Auteurs principaux: | , , , , |
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| Format: | Preprint |
| Publié: |
2025
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| Accès en ligne: | https://arxiv.org/abs/2507.04315 |
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| _version_ | 1866909942325182464 |
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| author | Zou, Qingyun Chen, Nuo Chen, Yao He, Bingsheng Wong, WengFei |
| author_facet | Zou, Qingyun Chen, Nuo Chen, Yao He, Bingsheng Wong, WengFei |
| contents | High-Level Synthesis (HLS) enables hardware design from C/C++ kernels but requires extensive transformations, such as restructuring code, inserting pragmas, adapting data types, and repairing non-synthesizable constructs, to achieve efficient FPGA implementations. While large language models (LLMs) show promise in automating these transformations, progress has been limited by the absence of large-scale, well-structured datasets. Existing HLS datasets focus primarily on resource estimation, lack paired C and HLS examples with testbenches, and cover only a narrow set of optimizations. We introduce HLStrans, the first benchmark-scale dataset for LLM-driven C-to-HLS synthesis. HLStrans contains over 124K paired C and HLS programs for real-world applications, with full testbenches and synthesis-based annotations of latency and resource usage. The dataset systematically captures five categories of transformations and is enriched by an automated augmentation pipeline combining LLMs, Monte Carlo Tree Search (MCTS), and Design Space Exploration (DSE). We benchmark state-of-the-art LLMs on HLStrans, demonstrating that retrieval and fine-tuning significantly improve success rates and performance. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2507_04315 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | HLStrans: Dataset for C-to-HLS Hardware Code Synthesis Zou, Qingyun Chen, Nuo Chen, Yao He, Bingsheng Wong, WengFei Hardware Architecture High-Level Synthesis (HLS) enables hardware design from C/C++ kernels but requires extensive transformations, such as restructuring code, inserting pragmas, adapting data types, and repairing non-synthesizable constructs, to achieve efficient FPGA implementations. While large language models (LLMs) show promise in automating these transformations, progress has been limited by the absence of large-scale, well-structured datasets. Existing HLS datasets focus primarily on resource estimation, lack paired C and HLS examples with testbenches, and cover only a narrow set of optimizations. We introduce HLStrans, the first benchmark-scale dataset for LLM-driven C-to-HLS synthesis. HLStrans contains over 124K paired C and HLS programs for real-world applications, with full testbenches and synthesis-based annotations of latency and resource usage. The dataset systematically captures five categories of transformations and is enriched by an automated augmentation pipeline combining LLMs, Monte Carlo Tree Search (MCTS), and Design Space Exploration (DSE). We benchmark state-of-the-art LLMs on HLStrans, demonstrating that retrieval and fine-tuning significantly improve success rates and performance. |
| title | HLStrans: Dataset for C-to-HLS Hardware Code Synthesis |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2507.04315 |