Voltage Mode Winner-Take-All Circuit for Neuromorphic Systems
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arXiv
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| Autores principales: | , |
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| Formato: | Preprint |
| Publicado: |
2025
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| _version_ | 1866918085102927872 |
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| author | Zyarah, Abdullah M. Kudithipudi, Dhireesha |
| author_facet | Zyarah, Abdullah M. Kudithipudi, Dhireesha |
| contents | Recent advances in neuromorphic computing demonstrate on-device learning capabilities with low power consumption. One of the key learning units in these systems is the winner-take-all circuit. In this research, we propose a winner-take-all circuit that can be configured to achieve k-winner and hysteresis properties, simulated in IBM 65 nm node. The circuit dissipated 34.9 $μ$W of power with a latency of 10.4 ns, while processing 1000 inputs. The utility of the circuit is demonstrated for spatial filtering and classification. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2507_04338 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Voltage Mode Winner-Take-All Circuit for Neuromorphic Systems Zyarah, Abdullah M. Kudithipudi, Dhireesha Artificial Intelligence Recent advances in neuromorphic computing demonstrate on-device learning capabilities with low power consumption. One of the key learning units in these systems is the winner-take-all circuit. In this research, we propose a winner-take-all circuit that can be configured to achieve k-winner and hysteresis properties, simulated in IBM 65 nm node. The circuit dissipated 34.9 $μ$W of power with a latency of 10.4 ns, while processing 1000 inputs. The utility of the circuit is demonstrated for spatial filtering and classification. |
| title | Voltage Mode Winner-Take-All Circuit for Neuromorphic Systems |
| topic | Artificial Intelligence |
| url | https://arxiv.org/abs/2507.04338 |