ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
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arXiv
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| Autores principales: | , , , , , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2025
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| Materias: | |
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| _version_ | 1866910117703712768 |
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| author | Chen, Zhirong Chang, Kaiyan Li, Zhuolin Li, Cangyuan He, Xinyang Chen, Chujie Wang, Mengdi Xu, Haobo Han, Yinhe Li, Huawei Wang, Ying |
| author_facet | Chen, Zhirong Chang, Kaiyan Li, Zhuolin Li, Cangyuan He, Xinyang Chen, Chujie Wang, Mengdi Xu, Haobo Han, Yinhe Li, Huawei Wang, Ying |
| contents | Large Language Models have emerged as powerful tools for automating Register-Transfer Level (RTL) code generation, yet they face critical limitations: existing approaches typically fail to simultaneously optimize functional correctness and hardware efficiency metrics such as Power, Performance, and Area (PPA). Methods relying on supervised fine-tuning commonly produce functionally correct but suboptimal designs due to the lack of inherent mechanisms for learning hardware optimization principles. Conversely, external post-processing techniques aiming to refine PPA performance after generation often suffer from inefficiency and do not improve the LLMs' intrinsic capabilities.
To overcome these challenges, we propose ChipSeek, a novel hierarchical reward based reinforcement learning framework designed to encourage LLMs to generate RTL code that is both functionally correct and optimized for PPA metrics. Our approach integrates direct feedback from EDA simulators and synthesis tools into a hierarchical reward mechanism, facilitating a nuanced understanding of hardware design trade-offs. Through Curriculum-Guided Dynamic Policy Optimization (CDPO), ChipSeek enhances the LLM's ability to generate high-quality, optimized RTL code. Evaluations on standard benchmarks demonstrate ChipSeek's superior performance, achieving state-of-the-art functional correctness and PPA performance. Furthermore, it excels in specific optimization tasks, consistently yielding highly efficient designs when individually targeting fine-grained optimization goals such as power, delay, and area. The artifact is open-source in https://github.com/rong-hash/chipseek. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2507_04736 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning Chen, Zhirong Chang, Kaiyan Li, Zhuolin Li, Cangyuan He, Xinyang Chen, Chujie Wang, Mengdi Xu, Haobo Han, Yinhe Li, Huawei Wang, Ying Artificial Intelligence Hardware Architecture Programming Languages Large Language Models have emerged as powerful tools for automating Register-Transfer Level (RTL) code generation, yet they face critical limitations: existing approaches typically fail to simultaneously optimize functional correctness and hardware efficiency metrics such as Power, Performance, and Area (PPA). Methods relying on supervised fine-tuning commonly produce functionally correct but suboptimal designs due to the lack of inherent mechanisms for learning hardware optimization principles. Conversely, external post-processing techniques aiming to refine PPA performance after generation often suffer from inefficiency and do not improve the LLMs' intrinsic capabilities. To overcome these challenges, we propose ChipSeek, a novel hierarchical reward based reinforcement learning framework designed to encourage LLMs to generate RTL code that is both functionally correct and optimized for PPA metrics. Our approach integrates direct feedback from EDA simulators and synthesis tools into a hierarchical reward mechanism, facilitating a nuanced understanding of hardware design trade-offs. Through Curriculum-Guided Dynamic Policy Optimization (CDPO), ChipSeek enhances the LLM's ability to generate high-quality, optimized RTL code. Evaluations on standard benchmarks demonstrate ChipSeek's superior performance, achieving state-of-the-art functional correctness and PPA performance. Furthermore, it excels in specific optimization tasks, consistently yielding highly efficient designs when individually targeting fine-grained optimization goals such as power, delay, and area. The artifact is open-source in https://github.com/rong-hash/chipseek. |
| title | ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning |
| topic | Artificial Intelligence Hardware Architecture Programming Languages |
| url | https://arxiv.org/abs/2507.04736 |