Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads
Fuente:
arXiv
Saved in:
| Main Authors: | , , , , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866917054119936000 |
|---|---|
| author | Kim, Jumin Baek, Seungmin Wi, Minbok Nam, Hwayong Kim, Michael Jaemin Lee, Sukhan Sohn, Kyomin Ahn, Jung Ho |
| author_facet | Kim, Jumin Baek, Seungmin Wi, Minbok Nam, Hwayong Kim, Michael Jaemin Lee, Sukhan Sohn, Kyomin Ahn, Jung Ho |
| contents | Per-Row Activation Counting (PRAC), a DRAM read disturbance mitigation method, modifies key DRAM timing parameters, reportedly causing significant performance overheads in simulator-based studies. However, given known discrepancies between simulators and real hardware, real-machine experiments are vital for accurate PRAC performance estimation. We present the first real-machine performance analysis of PRAC. After verifying timing modifications on the latest CPUs using microbenchmarks, our analysis shows that PRAC's average and maximum overheads are just 1.06% and 3.28% for the SPEC CPU2017 workloads -- up to 9.15x lower than simulator-based reports. Further, we show that the close page policy minimizes this overhead by effectively hiding the elongated DRAM row precharge operations due to PRAC from the critical path. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2507_05556 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads Kim, Jumin Baek, Seungmin Wi, Minbok Nam, Hwayong Kim, Michael Jaemin Lee, Sukhan Sohn, Kyomin Ahn, Jung Ho Hardware Architecture Cryptography and Security Per-Row Activation Counting (PRAC), a DRAM read disturbance mitigation method, modifies key DRAM timing parameters, reportedly causing significant performance overheads in simulator-based studies. However, given known discrepancies between simulators and real hardware, real-machine experiments are vital for accurate PRAC performance estimation. We present the first real-machine performance analysis of PRAC. After verifying timing modifications on the latest CPUs using microbenchmarks, our analysis shows that PRAC's average and maximum overheads are just 1.06% and 3.28% for the SPEC CPU2017 workloads -- up to 9.15x lower than simulator-based reports. Further, we show that the close page policy minimizes this overhead by effectively hiding the elongated DRAM row precharge operations due to PRAC from the critical path. |
| title | Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads |
| topic | Hardware Architecture Cryptography and Security |
| url | https://arxiv.org/abs/2507.05556 |