SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design
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arXiv
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| Format: | Preprint |
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2025
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| _version_ | 1866918086883409920 |
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| author | Alvanaki, Elisavet Lydia Lee, Kevin Carloni, Luca P. |
| author_facet | Alvanaki, Elisavet Lydia Lee, Kevin Carloni, Luca P. |
| contents | Over the last few years, Large Language Models (LLMs) have emerged as a valuable tool for Electronic Design Automation (EDA). State-of-the-art research in LLM-aided design has demonstrated the ability of LLMs to generate syntactically correct RTL code, showcasing encouraging prospects for integrating AI into the hardware design process. A key enabler of these advancements is the availability of high-quality benchmarks to evaluate new approaches. However, existing datasets and benchmarks fall short of system-level design, as they focus primarily on component-level information and low-complexity designs. To address this gap, we introduce the System-Level Design Benchmark (SLDB), a dataset tailored for evaluating LLMs in system-level integration and configuration tasks. SLDB includes a curated benchmark suite of 10 baseline SoC designs, whose components can be combined into an exponential number of distinct tile-based SoCs through a synthetic library. The dataset provides full SoC configurations, accelerator integration code, communication parameters, and accelerator-aware system configurations, along with testing-application code, compatible with the ESP platform[1]. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2507_06376 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design Alvanaki, Elisavet Lydia Lee, Kevin Carloni, Luca P. Hardware Architecture Over the last few years, Large Language Models (LLMs) have emerged as a valuable tool for Electronic Design Automation (EDA). State-of-the-art research in LLM-aided design has demonstrated the ability of LLMs to generate syntactically correct RTL code, showcasing encouraging prospects for integrating AI into the hardware design process. A key enabler of these advancements is the availability of high-quality benchmarks to evaluate new approaches. However, existing datasets and benchmarks fall short of system-level design, as they focus primarily on component-level information and low-complexity designs. To address this gap, we introduce the System-Level Design Benchmark (SLDB), a dataset tailored for evaluating LLMs in system-level integration and configuration tasks. SLDB includes a curated benchmark suite of 10 baseline SoC designs, whose components can be combined into an exponential number of distinct tile-based SoCs through a synthetic library. The dataset provides full SoC configurations, accelerator integration code, communication parameters, and accelerator-aware system configurations, along with testing-application code, compatible with the ESP platform[1]. |
| title | SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2507.06376 |