Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866909681294770176 |
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| author | Shen, Shan Yang, Dingcheng Xie, Yuyang Pei, Chunyan Yu, Wenjian Yu, Bei |
| author_facet | Shen, Shan Yang, Dingcheng Xie, Yuyang Pei, Chunyan Yu, Wenjian Yu, Bei |
| contents | To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulations, leading to difficulty in converging design parameters and excessive design iterations. Is it possible to well predict the parasitics based on the pre-layout circuit, so as to perform parasitic-aware pre-layout simulation? In this work, we propose a deep-learning-based 2-stage model to accurately predict these parasitics in pre-layout stages. The model combines a Graph Neural Network (GNN) classifier and Multi-Layer Perceptron (MLP) regressors, effectively managing class imbalance of the net parasitics in SRAM circuits. We also employ Focal Loss to mitigate the impact of abundant internal net samples and integrate subcircuit information into the graph to abstract the hierarchical structure of schematics. Experiments on 4 real SRAM designs show that our approach not only surpasses the state-of-the-art model in parasitic prediction by a maximum of 19X reduction of error but also significantly boosts the simulation process by up to 598X speedup. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2507_06549 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs Shen, Shan Yang, Dingcheng Xie, Yuyang Pei, Chunyan Yu, Wenjian Yu, Bei Machine Learning Hardware Architecture Systems and Control To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulations, leading to difficulty in converging design parameters and excessive design iterations. Is it possible to well predict the parasitics based on the pre-layout circuit, so as to perform parasitic-aware pre-layout simulation? In this work, we propose a deep-learning-based 2-stage model to accurately predict these parasitics in pre-layout stages. The model combines a Graph Neural Network (GNN) classifier and Multi-Layer Perceptron (MLP) regressors, effectively managing class imbalance of the net parasitics in SRAM circuits. We also employ Focal Loss to mitigate the impact of abundant internal net samples and integrate subcircuit information into the graph to abstract the hierarchical structure of schematics. Experiments on 4 real SRAM designs show that our approach not only surpasses the state-of-the-art model in parasitic prediction by a maximum of 19X reduction of error but also significantly boosts the simulation process by up to 598X speedup. |
| title | Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs |
| topic | Machine Learning Hardware Architecture Systems and Control |
| url | https://arxiv.org/abs/2507.06549 |