:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Authors:	Bhattacharyya, Shuvra S., Wolf, Marilyn
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	https://arxiv.org/abs/2507.09660
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints
by: Liao, Yuchao, et al.
Published: (2024)

HammerSim: A System-Level Tool to Model RowHammer
by: Goswami, Kaustav, et al.
Published: (2026)

FastCaps: A Design Methodology for Accelerating Capsule Network on Field Programmable Gate Arrays
by: Rahoof, Abdul, et al.
Published: (2025)

A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems
by: Bonet, Marc Solé i, et al.
Published: (2025)

ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
by: Li, Runkai, et al.
Published: (2025)

FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
by: Abi-Karam, Stefan, et al.
Published: (2025)

Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity
by: Duan, Cenlin, et al.
Published: (2024)

NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool
by: Bosbach, Nils, et al.
Published: (2022)

RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs
by: Kim, Jiho, et al.
Published: (2025)

AiEDA: Agentic AI Design Framework for Digital ASIC System Design
by: Patra, Aditya, et al.
Published: (2024)

DreamRAM: A Fine-Grained Configurable Design Space Modeling Tool for Custom 3D Die-Stacked DRAM
by: Cai, Victor, et al.
Published: (2025)

A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures
by: Curzel, Serena, et al.
Published: (2023)

Per-Bank Bandwidth Regulation of Shared Last-Level Cache for Real-Time Systems
by: Sullivan, Connor, et al.
Published: (2024)

A Sparsity-Aware Autonomous Path Planning Accelerator with HW/SW Co-Design and Multi-Level Dataflow Optimization
by: Zhang, Yifan, et al.
Published: (2025)

A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
by: Brignone, Giovanni, et al.
Published: (2023)

Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?
by: Sauter, Philippe, et al.
Published: (2024)

EN-T: Optimizing Tensor Computing Engines Performance via Encoder-Based Methodology
by: Wu, Qizhe, et al.
Published: (2024)

Optimal Clifford Initial States for Ising Hamiltonians
by: Bhattacharyya, Bikrant, et al.
Published: (2023)

AutoRAC: Automated Processing-in-Memory Accelerator Design for Recommender Systems
by: Cheng, Feng, et al.
Published: (2025)

Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding
by: Iff, Patrick, et al.
Published: (2026)

Deep Inverse Design for High-Level Synthesis
by: Chang, Ping, et al.
Published: (2024)

Mitigating the Bandwidth Wall via Data-Streaming System-Accelerator Co-Design
by: Liu, Qunyou, et al.
Published: (2026)

DFModel: Design Space Optimization of Large-Scale Systems Exploiting Dataflow Mappings
by: Ko, Sho, et al.
Published: (2024)

Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity
by: Duan, Cenlin, et al.
Published: (2025)

SPICE-PIDE: A Methodology for Design and Optimization of Integrated Circuits
by: Taraporewalla, Jehan, et al.
Published: (2024)

SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design
by: Alvanaki, Elisavet Lydia, et al.
Published: (2025)

DAE4HLS: Exposing Memory-Level Parallelism for High-Level Synthesis using Explicit Decoupling
by: Metz, David, et al.
Published: (2026)

OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
by: Sarkar, Rishov, et al.
Published: (2025)

From Circuits to SoC Processors: Arithmetic Approximation Techniques & Embedded Computing Methodologies for DSP Acceleration
by: Leon, Vasileios
Published: (2023)

CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design
by: Wan, Zishen, et al.
Published: (2025)

Towards Automated and Predictive Network-Level Energy Profiling in Reconfigurable IoT Systems
by: Bocus, Mohammud J., et al.
Published: (2025)

Dynamic Loop Fusion in High-Level Synthesis
by: Szafarczyk, Robert, et al.
Published: (2025)

HLSPilot: LLM-based High-Level Synthesis
by: Xiong, Chenwei, et al.
Published: (2024)

Low-Cost IoT-Enabled Tele-ECG Monitoring for Resource-Constrained Settings: System Design and Prototype
by: Neupane, Seemron, et al.
Published: (2026)

CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool
by: Andrulis, Tanner, et al.
Published: (2024)

Real Time FPGA Based CNNs for Detection, Classification, and Tracking in Autonomous Systems: State of the Art Designs and Optimizations
by: Sali, Safa Mohammed, et al.
Published: (2025)

A Paradigm for Generalized Multi-Level Priority Encoders
by: Phillips, Maxwell, et al.
Published: (2026)

ATLAAS: Automatic Tensor-Level Abstraction of Accelerator Semantics
by: Gao, Ruijie, et al.
Published: (2026)

CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems
by: Graening, Alexander, et al.
Published: (2025)

CktEvo: Repository-Level RTL Code Benchmark for Design Evolution
by: Shi, Zhengyuan, et al.
Published: (2026)