AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design
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arXiv
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| Auteurs principaux: | , , , , , , , |
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| Format: | Preprint |
| Publié: |
2025
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| _version_ | 1866915388305965056 |
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| author | Chen, Weiyu Liu, Chengjie Huang, Wenhao Lyu, Jinyang Yang, Mingqian Du, Yuan Du, Li Yang, Jun |
| author_facet | Chen, Weiyu Liu, Chengjie Huang, Wenhao Lyu, Jinyang Yang, Mingqian Du, Yuan Du, Li Yang, Jun |
| contents | Recent advancements have demonstrated the significant potential of large language models (LLMs) in analog circuit design. Nevertheless, testbench construction for analog circuits remains manual, creating a critical bottleneck in achieving fully automated design processes. Particularly when replicating circuit designs from academic papers, manual Testbench construction demands time-intensive implementation and frequent adjustments, which fails to address the dynamic diversity and flexibility requirements for automation. AnalogTester tackles automated analog design challenges through an LLM-powered pipeline: a) domain-knowledge integration, b) paper information extraction, c) simulation scheme synthesis, and d) testbench code generation with Tsinghua Electronic Design (TED). AnalogTester has demonstrated automated Testbench generation capabilities for three fundamental analog circuit types: operational amplifiers (op-amps), bandgap references (BGRs), and low-dropout regulators (LDOs), while maintaining a scalable framework for adaptation to broader circuit topologies. Furthermore, AnalogTester can generate circuit knowledge data and TED code corpus, establishing fundamental training datasets for LLM specialization in analog circuit design automation. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2507_09965 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design Chen, Weiyu Liu, Chengjie Huang, Wenhao Lyu, Jinyang Yang, Mingqian Du, Yuan Du, Li Yang, Jun Multiagent Systems Hardware Architecture Recent advancements have demonstrated the significant potential of large language models (LLMs) in analog circuit design. Nevertheless, testbench construction for analog circuits remains manual, creating a critical bottleneck in achieving fully automated design processes. Particularly when replicating circuit designs from academic papers, manual Testbench construction demands time-intensive implementation and frequent adjustments, which fails to address the dynamic diversity and flexibility requirements for automation. AnalogTester tackles automated analog design challenges through an LLM-powered pipeline: a) domain-knowledge integration, b) paper information extraction, c) simulation scheme synthesis, and d) testbench code generation with Tsinghua Electronic Design (TED). AnalogTester has demonstrated automated Testbench generation capabilities for three fundamental analog circuit types: operational amplifiers (op-amps), bandgap references (BGRs), and low-dropout regulators (LDOs), while maintaining a scalable framework for adaptation to broader circuit topologies. Furthermore, AnalogTester can generate circuit knowledge data and TED code corpus, establishing fundamental training datasets for LLM specialization in analog circuit design automation. |
| title | AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design |
| topic | Multiagent Systems Hardware Architecture |
| url | https://arxiv.org/abs/2507.09965 |