AssertCoder: LLM-Based Assertion Generation via Multimodal Specification Extraction
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arXiv
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| Main Authors: | , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866912481741373440 |
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| author | Tian, Enyuan Ci, Yiwei Yang, Qiusong Li, Yufeng Lyu, Zhichao |
| author_facet | Tian, Enyuan Ci, Yiwei Yang, Qiusong Li, Yufeng Lyu, Zhichao |
| contents | Assertion-Based Verification (ABV) is critical for ensuring functional correctness in modern hardware systems. However, manually writing high-quality SVAs remains labor-intensive and error-prone. To bridge this gap, we propose AssertCoder, a novel unified framework that automatically generates high-quality SVAs directly from multimodal hardware design specifications. AssertCoder employs a modality-sensitive preprocessing to parse heterogeneous specification formats (text, tables, diagrams, and formulas), followed by a set of dedicated semantic analyzers that extract structured representations aligned with signal-level semantics. These representations are utilized to drive assertion synthesis via multi-step chain-of-thought (CoT) prompting. The framework incorporates a mutation-based evaluation approach to assess assertion quality via model checking and further refine the generated assertions. Experimental evaluation across three real-world Register-Transfer Level (RTL) designs demonstrates AssertCoder's superior performance, achieving an average increase of 8.4% in functional correctness and 5.8% in mutation detection compared to existing state-of-the-art approaches. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2507_10338 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | AssertCoder: LLM-Based Assertion Generation via Multimodal Specification Extraction Tian, Enyuan Ci, Yiwei Yang, Qiusong Li, Yufeng Lyu, Zhichao Software Engineering Hardware Architecture Logic in Computer Science Assertion-Based Verification (ABV) is critical for ensuring functional correctness in modern hardware systems. However, manually writing high-quality SVAs remains labor-intensive and error-prone. To bridge this gap, we propose AssertCoder, a novel unified framework that automatically generates high-quality SVAs directly from multimodal hardware design specifications. AssertCoder employs a modality-sensitive preprocessing to parse heterogeneous specification formats (text, tables, diagrams, and formulas), followed by a set of dedicated semantic analyzers that extract structured representations aligned with signal-level semantics. These representations are utilized to drive assertion synthesis via multi-step chain-of-thought (CoT) prompting. The framework incorporates a mutation-based evaluation approach to assess assertion quality via model checking and further refine the generated assertions. Experimental evaluation across three real-world Register-Transfer Level (RTL) designs demonstrates AssertCoder's superior performance, achieving an average increase of 8.4% in functional correctness and 5.8% in mutation detection compared to existing state-of-the-art approaches. |
| title | AssertCoder: LLM-Based Assertion Generation via Multimodal Specification Extraction |
| topic | Software Engineering Hardware Architecture Logic in Computer Science |
| url | https://arxiv.org/abs/2507.10338 |