A mapping of the Min-Sum decoder to reduction operations, and its implementation using CUDA kernels
Fuente:
arXiv
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| Autores principales: | , |
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| Formato: | Preprint |
| Publicado: |
2025
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| _version_ | 1866908449069072384 |
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| author | Sella, Omer Shimon Heinis, Thomas |
| author_facet | Sella, Omer Shimon Heinis, Thomas |
| contents | Decoders for Low Density Parity Check (LDPC) codes are usually tailored to an application and optimized once the specific content and structure of the parity matrix are known. In this work we consider the parity matrix as an argument of the Min-Sum decoder, and provide a GPU implementation that is independent of the content of the parity matrix, and relies only on its dimensions. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2507_10424 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A mapping of the Min-Sum decoder to reduction operations, and its implementation using CUDA kernels Sella, Omer Shimon Heinis, Thomas Information Theory Decoders for Low Density Parity Check (LDPC) codes are usually tailored to an application and optimized once the specific content and structure of the parity matrix are known. In this work we consider the parity matrix as an argument of the Min-Sum decoder, and provide a GPU implementation that is independent of the content of the parity matrix, and relies only on its dimensions. |
| title | A mapping of the Min-Sum decoder to reduction operations, and its implementation using CUDA kernels |
| topic | Information Theory |
| url | https://arxiv.org/abs/2507.10424 |