Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2507.11150 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866912820926349312 |
|---|---|
| author | Bertagnon, Alessandro Dalpasso, Marcello Favalli, Michele Gavanelli, Marco |
| author_facet | Bertagnon, Alessandro Dalpasso, Marcello Favalli, Michele Gavanelli, Marco |
| contents | In the design of integrated circuits, one critical metric is the maximum delay introduced by combinational modules within the circuit. This delay is crucial because it represents the time required to perform a computation: in an Arithmetic-Logic Unit it represents the maximum time taken by the circuit to perform an arithmetic operation. When such a circuit is part of a larger, synchronous system, like a CPU, the maximum delay directly impacts the maximum clock frequency of the entire system. Typically, hardware designers use Static Timing Analysis to compute an upper bound of the maximum delay because it can be determined in polynomial time. However, relying on this upper bound can lead to suboptimal processor speeds, thereby missing performance opportunities. In this work, we tackle the challenging task of computing the actual maximum delay, rather than an approximate value. Since the problem is computationally hard, we model it in Answer Set Programming (ASP), a logic language featuring extremely efficient solvers. We propose non-trivial encodings of the problem into ASP. Experimental results show that ASP is a viable solution to address complex problems in hardware design. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2507_11150 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Fine-grained Timing Analysis of Digital Integrated Circuits in Answer Set Programming Bertagnon, Alessandro Dalpasso, Marcello Favalli, Michele Gavanelli, Marco Artificial Intelligence Logic in Computer Science In the design of integrated circuits, one critical metric is the maximum delay introduced by combinational modules within the circuit. This delay is crucial because it represents the time required to perform a computation: in an Arithmetic-Logic Unit it represents the maximum time taken by the circuit to perform an arithmetic operation. When such a circuit is part of a larger, synchronous system, like a CPU, the maximum delay directly impacts the maximum clock frequency of the entire system. Typically, hardware designers use Static Timing Analysis to compute an upper bound of the maximum delay because it can be determined in polynomial time. However, relying on this upper bound can lead to suboptimal processor speeds, thereby missing performance opportunities. In this work, we tackle the challenging task of computing the actual maximum delay, rather than an approximate value. Since the problem is computationally hard, we model it in Answer Set Programming (ASP), a logic language featuring extremely efficient solvers. We propose non-trivial encodings of the problem into ASP. Experimental results show that ASP is a viable solution to address complex problems in hardware design. |
| title | Fine-grained Timing Analysis of Digital Integrated Circuits in Answer Set Programming |
| topic | Artificial Intelligence Logic in Computer Science |
| url | https://arxiv.org/abs/2507.11150 |