Copertina

SystolicAttention: Fusing FlashAttention within a Single Systolic Array

Fuente: arXiv

Salvato in:

Dettagli Bibliografici
Autori principali:	Lin, Jiawei, Li, Yuanlong, Chen, Guokai, Bourgeat, Thomas
Natura:	Preprint
Pubblicazione:	2025
Soggetti:	Hardware Architecture Artificial Intelligence
Accesso online:	Acceder al recurso
Tags:	Aggiungi Tag Nessun Tag, puoi essere il primo ad aggiungerne!!

Documenti analoghi

FLASH-D: FlashAttention with Hidden Softmax Division
di: Alexandridis, Kosmas, et al.
Pubblicazione: (2025)

From Buffers to Registers: Unlocking Fine-Grained FlashAttention with Hybrid-Bonded 3D NPU Co-Design
di: Yu, Jinxin, et al.
Pubblicazione: (2026)

KAN-SAs: Efficient Acceleration of Kolmogorov-Arnold Networks on Systolic Arrays
di: Errabii, Sohaib, et al.
Pubblicazione: (2025)

Hybrid Systolic Array Accelerator with Optimized Dataflow for Edge Large Language Model Inference
di: Chen, Chun-Ting, et al.
Pubblicazione: (2025)

Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
di: Liu, Yuhao, et al.
Pubblicazione: (2026)

Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware Operators
di: Alexandridis, Kosmas, et al.
Pubblicazione: (2025)

TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Dataflow and Analytical Modelling
di: Sestito, Cristian, et al.
Pubblicazione: (2024)

SA-Kura: An Energy-Efficient Systolic Array Accelerator for Locally-Coupled Kuramoto Drift in Diffusion Sampling
di: Jin, Jeongmin, et al.
Pubblicazione: (2026)

SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
di: Taheri, Mahdi, et al.
Pubblicazione: (2024)

VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration
di: Helal, Shereef, et al.
Pubblicazione: (2025)

Explainable AI-Guided Efficient Approximate DNN Generation for Multi-Pod Systolic Arrays
di: Siddique, Ayesha, et al.
Pubblicazione: (2025)

FlexiSAGA: A Flexible Systolic Array GEMM Accelerator for Sparse and Dense Processing
di: Müller, Mika Markus, et al.
Pubblicazione: (2025)

Error Checking for Sparse Systolic Tensor Arrays
di: Peltekis, Christodoulos, et al.
Pubblicazione: (2024)

SISA: A Scale-In Systolic Array for GEMM Acceleration
di: Altamura, Luigi, et al.
Pubblicazione: (2026)

TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation
di: Sestito, Cristian, et al.
Pubblicazione: (2024)

Reducing the Cost of Dropout in Flash-Attention by Hiding RNG with GEMM
di: Ma, Haiyue, et al.
Pubblicazione: (2024)

H-FA: A Hybrid Floating-Point and Logarithmic Approach to Hardware Accelerated FlashAttention
di: Alexandridis, Kosmas, et al.
Pubblicazione: (2025)

Sim-FA: A GPGPU Simulator Framework for Fine-Grained FlashAttention Pipeline Analysis
di: Zhou, Zhongchun, et al.
Pubblicazione: (2026)

ADiP: Adaptive-Precision Systolic Array for Matrix Multiplication Acceleration
di: Abdelmaksoud, Ahmed J., et al.
Pubblicazione: (2025)

Systolic Array Data Flows for Efficient Matrix Multiplication in Deep Neural Networks
di: Raja, Tejas
Pubblicazione: (2024)

Periodic Online Testing for Sparse Systolic Tensor Arrays
di: Peltekis, Christodoulos, et al.
Pubblicazione: (2025)

Systolic Array Acceleration of Diagonal-Optimized Sparse-Sparse Matrix Multiplication for Efficient Quantum Simulation
di: Su, Yuchao, et al.
Pubblicazione: (2025)

Single-Event Upset Analysis of a Systolic Array based Deep Neural Network Accelerator
di: Jonckers, Naïn, et al.
Pubblicazione: (2024)

FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inference
di: Cherezova, Natalia, et al.
Pubblicazione: (2025)

ReDas: A Lightweight Architecture for Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic Array
di: Han, Meng, et al.
Pubblicazione: (2023)

Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
di: Taheri, Mahdi, et al.
Pubblicazione: (2024)

Revealing Untapped DSP Optimization Potentials for FPGA-Based Systolic Matrix Engines
di: Li, Jindong, et al.
Pubblicazione: (2024)

Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems
di: Palacios, Pedro, et al.
Pubblicazione: (2024)

SWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs
di: Bai, Zhenyu, et al.
Pubblicazione: (2024)

ENFOR-SA: End-to-end Cross-layer Transient Fault Injector for Efficient and Accurate DNN Reliability Assessment on Systolic Arrays
di: Tonetto, Rafael Billig, et al.
Pubblicazione: (2026)

A Tensor-Train Decomposition based Compression of LLMs on Group Vector Systolic Accelerator
di: Huang, Sixiao, et al.
Pubblicazione: (2025)

MAGNet: A Multi-Scale Attention-Guided Graph Fusion Network for DRC Violation Detection
di: Lu, Weihan, et al.
Pubblicazione: (2025)

ONE-SA: Enabling Nonlinear Operations in Systolic Arrays for Efficient and Flexible Neural Network Inference
di: Sun, Ruiqi, et al.
Pubblicazione: (2024)

Salca: A Sparsity-Aware Hardware Accelerator for Efficient Long-Context Attention Decoding
di: Fan, Wang, et al.
Pubblicazione: (2026)

Sequence-Aware Split Heuristic to Mitigate SM Underutilization in FlashAttention-3 Low-Head-Count Decoding
di: Font, Martí Llopart, et al.
Pubblicazione: (2026)

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration
di: Taka, Endri, et al.
Pubblicazione: (2025)

Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters
di: Mazzola, Sergio, et al.
Pubblicazione: (2024)

Rethinking LLM Inference Bottlenecks: Insights from Latent Attention and Mixture-of-Experts
di: Yun, Sungmin, et al.
Pubblicazione: (2025)

TReX- Reusing Vision Transformer's Attention for Efficient Xbar-based Computing
di: Moitra, Abhishek, et al.
Pubblicazione: (2024)

Static IR Drop Prediction with Attention U-Net and Saliency-Based Explainability
di: Zhang, Lizi, et al.
Pubblicazione: (2024)