Cover Image

Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage

Fuente: arXiv
Saved in:
Bibliographic Details
Main Authors: Pun, Junius, Dai, Xilai, Zgheib, Grace, Iyer, Mahesh A., Boutros, Andrew, Betz, Vaughn, Abdelfattah, Mohamed S.
Format: Preprint
Published: 2025
Subjects:
Hardware Architecture
Online Access:
Acceder al recurso
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Description not available.

Similar Items