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Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage

Fuente: arXiv

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Bibliographic Details
Main Authors:	Pun, Junius, Dai, Xilai, Zgheib, Grace, Iyer, Mahesh A., Boutros, Andrew, Betz, Vaughn, Abdelfattah, Mohamed S.
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
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